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AgeCommit message (Expand)AuthorFilesLines
2018-11-27Misc. address translation clarificationsAndrew Waterman1-7/+7
2018-11-26Clarify that bits 16 and up of *ip/*ie are "custom"Andrew Waterman1-14/+18
2018-11-21Clarify that mtimecmp writes aren't synchronous with MTIP readsAndrew Waterman1-0/+12
2018-11-21note that xtval is written upon a trapAndrew Waterman1-1/+3
2018-11-21Add counter-inhibit mechanismAndrew Waterman1-0/+64
2018-11-21fix typosAndrew Waterman1-2/+2
2018-11-09WFI is not a HINTAndrew Waterman1-2/+2
2018-11-06spelling20181106-Base-RatificationAndrew Waterman1-1/+1
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman1-2/+9
2018-10-02Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-7/+5
2018-09-26Custom interrupt priorities are customAndrew Waterman1-4/+4
2018-09-24SFENCE behavior is independent of privilege modeAndrew Waterman1-3/+1
2018-09-24Improving lanuage.Krste Asanovic1-4/+4
2018-09-23Unused PMP fields are WARL 0, not WIRIAndrew Waterman1-2/+2
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman1-4/+4
2018-09-23unused misa fields are wlrl, not wiriAndrew Waterman1-1/+1
2018-09-23Fix an off-by-one error in defining coarse-grained PMPs for NAPOTAndrew Waterman1-6/+7
2018-09-23hart IDs must be uniqueAndrew Waterman1-1/+1
2018-08-31Removed text that implied there was a maximum alignment requirementKrste Asanovic1-2/+9
2018-08-29Generalized description of counter behavior when not accessible.Krste Asanovic1-3/+1
2018-08-29Clarify that mtval/mepc are set on interrupts, tooAndrew Waterman1-4/+4
2018-08-26Clarified that counter-enable fields don't change underlying counter values.Krste Asanovic1-0/+6
2018-08-12Fix typoAndrew Waterman1-1/+1
2018-08-09Added specification that xRET instructions may, but are notKrste Asanovic1-0/+11
2018-08-06Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignme...Rishiyur S. Nikhil1-1/+1
2018-07-30clarificationKrste Asanovic1-1/+1
2018-07-15Reverting what would have been unintended change in spec. InterruptsKrste Asanovic1-12/+14
2018-07-13Clarified description of interrupt enables across multiple privilege modes.Krste Asanovic1-8/+19
2018-07-11Clarify the behavior of M-mode hardware performance counters.Krste Asanovic1-7/+10
2018-07-06Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)Alexandre Joannou1-4/+9
2018-06-11Explicitly mention that FS may be imprecise (#192)Andrew Waterman1-0/+13
2018-05-25PMP changes need an SFENCE when VM is enabledAndrew Waterman1-0/+25
2018-05-06Luke's feedbackAndrew Waterman1-1/+2
2018-05-02Updates to the memory consistency model specDaniel Lustig1-4/+5
2018-05-02Clarify URET with no user-mode traps support (#164)Alexandre Joannou1-2/+4
2018-05-02Fix typoAndrew Waterman1-1/+1
2018-04-19Use G for PMP granularity, not LAndrew Waterman1-5/+5
2018-04-13Remove hyphen from M-XLEN etc.Andrew Waterman1-28/+28
2018-04-13Clarifications re: writable XLENAndrew Waterman1-3/+11
2018-04-13Resolve XLEN vs. M-XLEN ambiguitiesAndrew Waterman1-58/+61
2018-04-03Fix description of PMP granularity probing mechanismAndrew Waterman1-3/+3
2018-04-03Specify coarser-than-4-byte PMP semanticsAndrew Waterman1-0/+15
2018-03-31Improve interrupt priority commentaryAndrew Waterman1-7/+3
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-12/+12
2018-02-22Fix mepc/sepc definitions w.r.t. IALIGNAndrew Waterman1-8/+2
2018-02-22Tweak wording of misa.C proposalAndrew Waterman1-2/+3
2018-02-22Introduce IALIGN; propose misa.C semanticsAndrew Waterman1-3/+10
2018-01-23Added commentary on fixed interrupt priority scheme for mip/mie.Krste Asanovic1-0/+42
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