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AgeCommit message (Expand)AuthorFilesLines
2017-04-27Improve ECALL textAndrew Waterman1-1/+1
2017-04-27Describe ECALL/EBREAK operation in privileged architectureAndrew Waterman1-1/+49
2017-04-20Make mcause table easier to understandAndrew Waterman1-6/+6
2017-04-20Improve stval/mtval warl textAndrew Waterman1-5/+8
2017-04-17mepc, sepc, mtval, and stval are WARLAndrew Waterman1-0/+10
2017-04-11mtval/stval are zeroed for other exceptionsAndrew Waterman1-1/+2
2017-04-11Clarify [s/m][epc/tval/cause] are only written on exceptions into that modeAndrew Waterman1-6/+19
2017-04-11SPTBR -> SATPAndrew Waterman1-2/+2
2017-04-10Clarify WFI w.r.t. interrupt delegationAndrew Waterman1-4/+5
2017-04-09Fix typoAndrew Waterman1-1/+1
2017-04-07Add vectored interruptsAndrew Waterman1-17/+40
2017-03-31Incorporate PMP feedbackAndrew Waterman1-2/+5
2017-03-31Commentary on 'mtval' refers to 'mtbadinst' instead of 'mtval'Michael Clark1-1/+1
2017-03-30Modify PMP encoding and improve descriptionAndrew Waterman1-67/+59
2017-03-30PMP cleanupAndrew Waterman1-6/+8
2017-03-29Clarify that misaligned accesses violating PMPs become partially visibleAndrew Waterman1-3/+11
2017-03-29Improve PMP sectionAndrew Waterman1-41/+237
2017-03-28First draft of PMP specAndrew Waterman1-20/+149
2017-03-28Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...Krste Asanovic1-18/+18
2017-03-28Separate access faults from VM faultsAndrew Waterman1-5/+17
2017-03-27Added David Horner's suggestion of faster way to test for base ISA width if m...Krste Asanovic1-2/+4
2017-03-26Replaced mbadaddr with mbadbits register, which can now capture badKrste Asanovic1-12/+62
2017-03-24Simplified MXL/SXL/UXL design. Now, no checks for monotonically decreasing X...Krste Asanovic1-36/+53
2017-03-20Small changes.Krste Asanovic1-5/+5
2017-03-20Specify encoding of mvendorid fieldAndrew Waterman1-4/+16
2017-03-20Changed mvendorid to hold the JEDEC manufacturer code for the core vendor as ...Krste Asanovic1-6/+9
2017-03-20Now mideleg /medeleg only exist if lower privilege mode exists and can take t...Krste Asanovic1-2/+9
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman1-15/+16
2017-03-19Excised H-mode from spec.Krste Asanovic1-177/+171
2017-03-18Software shouldn't use misaligned accesses on non-idempotent regionsAndrew Waterman1-0/+7
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman1-2/+2
2017-03-13Add TSR mechanismAndrew Waterman1-6/+21
2017-03-07Update UXL/SXL languageAndrew Waterman1-25/+21
2017-03-07Make some supervisor fields WPRIAndrew Waterman1-1/+1
2017-03-06fix typoAndrew Waterman1-1/+1
2017-03-03misa Base => MXLAndrew Waterman1-14/+14
2017-03-01Added placeholder for J extension.Krste Asanovic1-1/+1
2017-02-26Add TW bitAndrew Waterman1-12/+24
2017-02-26Incorporate more Hauser feedbackAndrew Waterman1-6/+11
2017-02-26SX -> SXLAndrew Waterman1-23/+23
2017-02-24Incorporate most of Hauser's feedbackAndrew Waterman1-6/+141
2017-02-24Clarify that traps don't delegate downwardsAndrew Waterman1-0/+8
2017-02-23Clarify FS=Off behaviorAndrew Waterman1-3/+6
2017-02-20mhcounteren -> mcounteren; mucounteren -> scounterenAndrew Waterman1-16/+26
2017-02-13Remove mstatus.VM, Mbb, Mbbid; add sptbr.MODEAndrew Waterman1-268/+4
2017-02-01Reorganize directory structureAndrew Waterman1-0/+2312
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