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AgeCommit message (Expand)AuthorFilesLines
2021-01-13Explain rationale for seting xPP=U on an xRETAndrew Waterman1-1/+7
2021-01-13Clean up NMI/mepc wordingAndrew Waterman1-2/+2
2021-01-12Additional FS clarificationAndrew Waterman1-1/+1
2021-01-12spell checkAndrew Waterman1-1/+1
2021-01-12clarify that FS need only be set to dirty if the state is actually changedAndrew Waterman1-0/+4
2020-12-22Make unused misa fields 0 (WARL) rather than WLRL. (#615)Paul Donahue1-1/+1
2020-11-19Dedicated section for machine-level memory-mapped registers (not standard CSR...Alexandre Joannou1-114/+116
2020-11-06PMP uses physical addresses (not effective addresses) (#610)Paul Donahue1-2/+2
2020-10-27mcounteren is WARLAndrew Waterman1-0/+4
2020-10-25PMP TOR clarificationsAndrew Waterman1-1/+8
2020-10-18Another attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-17Attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-13Both HWBPs and EBREAKs populate mtval (#601)Andrew Waterman1-1/+1
2020-10-06For emphasis, make MXR/SUM commentary normativeAndrew Waterman1-2/+0
2020-09-30Disabling and reenabling extensions makes their state unspecified (#585)Andrew Waterman1-0/+4
2020-09-29Clarify behavior when an extension is disabled (#592)gfavor1-0/+2
2020-09-28Clarify that "exception code" is used for both exceptions and interruptsAndrew Waterman1-1/+1
2020-09-01PMP changes don't need an sfence only when page-based virtual memory is not i...gfavor1-1/+1
2020-08-25Change "hardwired to other field" to "read-only field" (#571)John Hauser1-9/+9
2020-08-25Rename empty regions to vacant regions for consistency with unpriv specAndrew Waterman1-4/+4
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-4/+4
2020-08-12mcounteren only exists if U-mode existsAndrew Waterman1-0/+2
2020-08-03Fix formatting of 2^XLENAndrew Waterman1-5/+5
2020-07-22Pmp wording fix (#545)Stef O'Rear1-4/+4
2020-07-17Remove redundant phrase from access-/page-fault textAndrew Waterman1-1/+1
2020-06-10Priority of misaligned load/store address checks is implementation-definedAndrew Waterman1-1/+18
2020-06-04Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d845515...Andrew Waterman1-1/+1
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman1-27/+46
2020-05-05Clarify that _coherent_ main memory regions use RVWMO or RVTSOAndrew Waterman1-2/+4
2020-04-22Clarify that mtimecmp comparison is unsignedAndrew Waterman1-3/+4
2020-04-22Clarify that various reset events are relative to hart resetAndrew Waterman1-4/+4
2020-04-17Clarify that RV64 accesses to mtime/mtimecmp are atomicAndrew Waterman1-0/+3
2020-04-14Avoid "should" when describing a mandateAndrew Waterman1-2/+2
2020-03-23PMP reset values are now platform-definedAndrew Waterman1-2/+4
2020-03-03Clarified overflow behavior of mtime register.Krste Asanovic1-3/+4
2020-03-02Make clear that "store exception" is "store/AMO exception".Krste Asanovic1-1/+1
2020-03-02Clarify which exceptions are raised by LR/SC/AMOAndrew Waterman1-0/+4
2020-02-12Incorporate Andy Glew's commentsAndrew Waterman1-4/+3
2020-02-12Only describe scounteren in supervisor chapterAndrew Waterman1-19/+7
2020-01-24Clarify mvendorid.Bank vs. JEDEC bank numberAndrew Waterman1-0/+6
2020-01-20ignore write to "controlled" SBE and UBE. (#477)David-Horner1-2/+2
2020-01-08Clarified that NMIs are interrupts, and should set mcause to have high bit set.Krste Asanovic1-3/+5
2020-01-07Fix PDF searching by changing e.g. {\em x}\,IE to {\em x}\/IEAndrew Waterman1-24/+24
2020-01-06Make mtimecmp code sequence legalAndrew Waterman1-3/+4
2019-12-24Rephrase awkward sentenceAndrew Waterman1-2/+3
2019-11-19MRET and SRET clear MPRV when leaving M-modeAndrew Waterman1-4/+4
2019-11-06Convert samepage-commentary blocks to commentary blocksAndrew Waterman1-2/+2
2019-10-22Merge branch 'unspecified' of https://github.com/pdonahue-ventana/riscv-isa-m...Andrew Waterman1-1/+1
2019-10-02Add a description of the reservability PMA.Josh Scheid1-9/+32
2019-10-02Clarify that pmpcfg.L takes effect even when pmpcfg.A=0Andrew Waterman1-0/+4
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