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2019-02-13Fix typos. (#340)Josh Scheid1-2/+2
2019-02-01Make the mcause table easier to find.Prashanth Mundkur1-2/+2
2019-01-29Fix a couple of typos and inconsistencies. (#334)Prashanth Mundkur1-6/+6
2019-01-28Forgot to indicate that mstatus.FS is a WARL field.Andrew Waterman1-1/+1
2019-01-22Nest mstatus subsectionsAndrew Waterman1-5/+5
h/t Dan Hopper
2018-12-27Clarify that writing pmpcfg does not alter pmpaddr's underlying valueAndrew Waterman1-0/+4
Closes #320.
2018-12-26Rephrase NA4 restrictionAndrew Waterman1-1/+1
Closes #321
2018-12-21tweaksAndrew Waterman1-3/+2
2018-12-10fix typosAndrew Waterman1-2/+2
2018-12-04Version of priv spec ready for ratification processAndrew Waterman1-1/+11
2018-12-03Mostly remove RV128 from priv spec, for nowAndrew Waterman1-26/+30
2018-12-03Remove config string chapter for nowAndrew Waterman1-6/+2
2018-12-03M-mode editsAndrew Waterman1-27/+22
2018-12-02Remove PLIC chapter from privileged specAndrew Waterman1-2/+1
2018-12-02WIP on M-mode chapterAndrew Waterman1-29/+10
2018-12-02Clarify misaligned-AMO emulation schemeAndrew Waterman1-9/+17
2018-12-02Use date-based versioning scheme for priv specAndrew Waterman1-1/+1
2018-11-30Hauser commentsAndrew Waterman1-15/+13
2018-11-30Extend mstatus.TW to U-mode for M/U systems (#286)Andrew Waterman1-6/+14
2018-11-30Interrupts 16 and above are platform-definedAndrew Waterman1-4/+4
Platforms may avail them for custom use.
2018-11-30Revert "Clarify that bits 16 and up of *ip/*ie are "custom""Andrew Waterman1-18/+14
This reverts commit 6e34c135660bee09210c1af2c9502042f0998f44.
2018-11-30Define semantics for contradictory misa settings (#285)Andrew Waterman1-0/+16
* Define semantics for contradictory misa settings Closes #82 * Add commentary about contradictor misa settings
2018-11-27Add commentary about MPRV and writable XLENAndrew Waterman1-0/+5
Closes #107
2018-11-27Extension XS fields might not be in mstatusAndrew Waterman1-1/+1
Fixes #64
2018-11-27Misc. address translation clarificationsAndrew Waterman1-7/+7
Courtesy @gameboo in #205
2018-11-26Clarify that bits 16 and up of *ip/*ie are "custom"Andrew Waterman1-14/+18
Closes #271.
2018-11-21Clarify that mtimecmp writes aren't synchronous with MTIP readsAndrew Waterman1-0/+12
2018-11-21note that xtval is written upon a trapAndrew Waterman1-1/+3
2018-11-21Add counter-inhibit mechanismAndrew Waterman1-0/+64
2018-11-21fix typosAndrew Waterman1-2/+2
2018-11-09WFI is not a HINTAndrew Waterman1-2/+2
2018-11-06spelling20181106-Base-RatificationAndrew Waterman1-1/+1
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
Rationale is provided in the unprivileged manual (counters.tex). Resolves #249
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman1-2/+9
* Clarify interrupt delegation semantics * Update contributors
2018-10-02Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-7/+5
2018-09-26Custom interrupt priorities are customAndrew Waterman1-4/+4
2018-09-24SFENCE behavior is independent of privilege modeAndrew Waterman1-3/+1
2018-09-24Improving lanuage.Krste Asanovic1-4/+4
Closed #215
2018-09-23Unused PMP fields are WARL 0, not WIRIAndrew Waterman1-2/+2
2018-09-23unused mip fields are wpri instead of wiriAndrew Waterman1-4/+4
2018-09-23unused misa fields are wlrl, not wiriAndrew Waterman1-1/+1
2018-09-23Fix an off-by-one error in defining coarse-grained PMPs for NAPOTAndrew Waterman1-6/+7
2018-09-23hart IDs must be uniqueAndrew Waterman1-1/+1
2018-08-31Removed text that implied there was a maximum alignment requirementKrste Asanovic1-2/+9
for mtvec, and clarified that different modes can have different mtvec alignment constraints.
2018-08-29Generalized description of counter behavior when not accessible.Krste Asanovic1-3/+1
2018-08-29Clarify that mtval/mepc are set on interrupts, tooAndrew Waterman1-4/+4
2018-08-26Clarified that counter-enable fields don't change underlying counter values.Krste Asanovic1-0/+6
2018-08-12Fix typoAndrew Waterman1-1/+1
2018-08-09Added specification that xRET instructions may, but are notKrste Asanovic1-0/+11
required to, clear LR reservations if A extension present.
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