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2018-08-06Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignme...Rishiyur S. Nikhil1-1/+1
2018-07-30clarificationKrste Asanovic1-1/+1
2018-07-15Reverting what would have been unintended change in spec. InterruptsKrste Asanovic1-12/+14
2018-07-13Clarified description of interrupt enables across multiple privilege modes.Krste Asanovic1-8/+19
2018-07-11Clarify the behavior of M-mode hardware performance counters.Krste Asanovic1-7/+10
2018-07-06Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)Alexandre Joannou1-4/+9
2018-06-11Explicitly mention that FS may be imprecise (#192)Andrew Waterman1-0/+13
2018-05-25PMP changes need an SFENCE when VM is enabledAndrew Waterman1-0/+25
2018-05-06Luke's feedbackAndrew Waterman1-1/+2
2018-05-02Updates to the memory consistency model specDaniel Lustig1-4/+5
2018-05-02Clarify URET with no user-mode traps support (#164)Alexandre Joannou1-2/+4
2018-05-02Fix typoAndrew Waterman1-1/+1
2018-04-19Use G for PMP granularity, not LAndrew Waterman1-5/+5
2018-04-13Remove hyphen from M-XLEN etc.Andrew Waterman1-28/+28
2018-04-13Clarifications re: writable XLENAndrew Waterman1-3/+11
2018-04-13Resolve XLEN vs. M-XLEN ambiguitiesAndrew Waterman1-58/+61
2018-04-03Fix description of PMP granularity probing mechanismAndrew Waterman1-3/+3
2018-04-03Specify coarser-than-4-byte PMP semanticsAndrew Waterman1-0/+15
2018-03-31Improve interrupt priority commentaryAndrew Waterman1-7/+3
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman1-12/+12
2018-02-22Fix mepc/sepc definitions w.r.t. IALIGNAndrew Waterman1-8/+2
2018-02-22Tweak wording of misa.C proposalAndrew Waterman1-2/+3
2018-02-22Introduce IALIGN; propose misa.C semanticsAndrew Waterman1-3/+10
2018-01-23Added commentary on fixed interrupt priority scheme for mip/mie.Krste Asanovic1-0/+42
2018-01-23Clarified when mip/mie bits are hardwired to zero when user mode present.Krste Asanovic1-1/+2
2018-01-23Use y instead of a in PMP addressesAndrew Waterman1-8/+8
2017-12-27Admit that the V extension existsAndrew Waterman1-2/+2
2017-12-12Describe optional support for misaligned AMOs (#117)Andrew Waterman1-0/+15
2017-12-12hcounteren doesn't existAndrew Waterman1-1/+1
2017-12-11Fix xIE descriptive errorAndrew Waterman1-1/+1
2017-11-12Mark useless PMP NAPOT case as reservedAndrew Waterman1-0/+1
2017-11-09Make MPP/SPP WARL fieldsAndrew Waterman1-3/+6
2017-11-09State that writable-but-not-readable PMPs are reservedAndrew Waterman1-1/+2
2017-11-09Specify meaning of R/W/X bits in PMPAndrew Waterman1-0/+8
2017-11-09Add hypervisor draft proposalAndrew Waterman1-1/+1
2017-11-09fix typosAndrew Waterman1-1/+1
2017-10-30tweak wordingAndrew Waterman1-1/+1
2017-10-20Specify that user-ISA LR/SC constraints apply to main memoryAndrew Waterman1-0/+8
2017-10-20Put the onus on software to align pc/epc when clearing misa.CAndrew Waterman1-0/+3
2017-10-11Fix outdated commentary on mcounterenAndrew Waterman1-2/+2
2017-09-20Clarify mtval; allow platform to specify when it's writtenAndrew Waterman1-8/+14
2017-09-20Describe MSIE/SSIE/USIEAndrew Waterman1-0/+4
2017-08-17Always order interrupt priority by privilege modeAndrew Waterman1-2/+2
2017-08-15Clarify interrupt priority orderAndrew Waterman1-3/+2
2017-08-15Fix typo in mideleg caption (#98)stkaplan1-1/+1
2017-07-30clarify that more-privileged interrupts are of higher priorityAndrew Waterman1-4/+6
2017-06-26Fix typo in PMP address CSR bit field diagramRichard Xia1-1/+1
2017-06-12Fix word case, typos and word choicePaul Wise1-1/+1
2017-06-05Reserve mip/mie bits below 16 for standard useAndrew Waterman1-6/+4
2017-06-03Forbid S-mode execution from user memoryJacob Bachmeyer1-1/+1
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