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AgeCommit message (Expand)AuthorFilesLines
2019-04-19Don't reference the SBI in normative privileged spec sectionsAndrew Waterman1-14/+6
2019-04-11clarify in commentary that environment break == EBREAKAndrew Waterman1-1/+1
2019-04-11Explain when sideleg/sedeleg must existAndrew Waterman1-0/+6
2019-04-08Elucidate two uses of the word "error"Andrew Waterman1-1/+1
2019-04-05mtime is a read-write registerAndrew Waterman1-1/+1
2019-03-28mhpmcounters are WARLAndrew Waterman1-1/+7
2019-03-26Minor grammar fix (#357)pdonahue-ventana1-1/+1
2019-03-15Add more MXR/SUM commentaryAndrew Waterman1-0/+6
2019-03-13Improve synchronous exception priority table/descriptionAndrew Waterman1-18/+19
2019-03-13Clarify which exception is raised in two casesAndrew Waterman1-2/+2
2019-03-12Specify synchronous exception priority orderingAndrew Waterman1-0/+46
2019-03-07Update mcause/scause tables to allocate some custom exception causesAndrew Waterman1-6/+11
2019-02-22Add misa to reset sectionAndrew Waterman1-1/+5
2019-02-13Fix typos. (#340)Josh Scheid1-2/+2
2019-02-01Make the mcause table easier to find.Prashanth Mundkur1-2/+2
2019-01-29Fix a couple of typos and inconsistencies. (#334)Prashanth Mundkur1-6/+6
2019-01-28Forgot to indicate that mstatus.FS is a WARL field.Andrew Waterman1-1/+1
2019-01-22Nest mstatus subsectionsAndrew Waterman1-5/+5
2018-12-27Clarify that writing pmpcfg does not alter pmpaddr's underlying valueAndrew Waterman1-0/+4
2018-12-26Rephrase NA4 restrictionAndrew Waterman1-1/+1
2018-12-21tweaksAndrew Waterman1-3/+2
2018-12-10fix typosAndrew Waterman1-2/+2
2018-12-04Version of priv spec ready for ratification processAndrew Waterman1-1/+11
2018-12-03Mostly remove RV128 from priv spec, for nowAndrew Waterman1-26/+30
2018-12-03Remove config string chapter for nowAndrew Waterman1-6/+2
2018-12-03M-mode editsAndrew Waterman1-27/+22
2018-12-02Remove PLIC chapter from privileged specAndrew Waterman1-2/+1
2018-12-02WIP on M-mode chapterAndrew Waterman1-29/+10
2018-12-02Clarify misaligned-AMO emulation schemeAndrew Waterman1-9/+17
2018-12-02Use date-based versioning scheme for priv specAndrew Waterman1-1/+1
2018-11-30Hauser commentsAndrew Waterman1-15/+13
2018-11-30Extend mstatus.TW to U-mode for M/U systems (#286)Andrew Waterman1-6/+14
2018-11-30Interrupts 16 and above are platform-definedAndrew Waterman1-4/+4
2018-11-30Revert "Clarify that bits 16 and up of *ip/*ie are "custom""Andrew Waterman1-18/+14
2018-11-30Define semantics for contradictory misa settings (#285)Andrew Waterman1-0/+16
2018-11-27Add commentary about MPRV and writable XLENAndrew Waterman1-0/+5
2018-11-27Extension XS fields might not be in mstatusAndrew Waterman1-1/+1
2018-11-27Misc. address translation clarificationsAndrew Waterman1-7/+7
2018-11-26Clarify that bits 16 and up of *ip/*ie are "custom"Andrew Waterman1-14/+18
2018-11-21Clarify that mtimecmp writes aren't synchronous with MTIP readsAndrew Waterman1-0/+12
2018-11-21note that xtval is written upon a trapAndrew Waterman1-1/+3
2018-11-21Add counter-inhibit mechanismAndrew Waterman1-0/+64
2018-11-21fix typosAndrew Waterman1-2/+2
2018-11-09WFI is not a HINTAndrew Waterman1-2/+2
2018-11-06spelling20181106-Base-RatificationAndrew Waterman1-1/+1
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-10-09Clarify interrupt delegation semantics (#158)Andrew Waterman1-2/+9
2018-10-02Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-7/+5
2018-09-26Custom interrupt priorities are customAndrew Waterman1-4/+4
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