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2021-09-15RISC-V Foundation -> RISC-V InternationalAndrew Waterman1-2/+2
2021-09-10Speculative implicit reads, v2 (#724)Andrew Waterman1-2/+1
2021-08-30Revert "Replace "EEI" with "execution environment" (#723)"Andrew Waterman1-26/+17
2021-08-28Replace "EEI" with "execution environment" (#723)John Hauser1-17/+26
2021-05-23Fix hyphenationAndrew Waterman1-1/+1
2020-08-14Improve table of trap characteristics in introduction (#562)John Hauser1-6/+8
2020-08-03Fix formatting of 2^XLENAndrew Waterman1-3/+3
2020-07-22Pmp wording fix (#545)Stef O'Rear1-7/+7
2020-03-01Merge pull request #413 from marceg/gauthierm-customKrste Asanovic1-11/+15
2020-01-13Correct left double quotes (#475)ansimita1-1/+1
2019-11-06Convert samepage-commentary blocks to commentary blocksAndrew Waterman1-2/+2
2019-10-22Merge branch 'unspecified' of https://github.com/pdonahue-ventana/riscv-isa-m...Andrew Waterman1-0/+19
2019-07-26The execution environment must guarantee harts make progressAndrew Waterman1-0/+17
2019-07-19Clarify and define categories of extensions.Marc Gauthier1-11/+15
2019-06-21Changes to unprivileged spec for bi[g]-endian supportAndrew Waterman1-11/+27
2019-05-04Typos (#379)Alexandre Joannou1-1/+1
2019-05-03Added UNSPECIFIEDPaul Donahue1-7/+7
2019-05-01Introduce the term UNSPECIFIED.Paul Donahue1-0/+19
2018-12-21Address space is circularAndrew Waterman1-1/+7
2018-12-20Clean up naming and define G = IMAFDZicsr_ZifenceiAndrew Waterman1-4/+2
2018-11-30Be more tentativeAndrew Waterman1-4/+4
2018-11-3048+-bit instruction-length encoding scheme is not frozenAndrew Waterman1-11/+19
2018-11-28Memory section tweaksAndrew Waterman1-2/+2
2018-11-28Memory section editsAndrew Waterman1-12/+40
2018-11-27Add Hauser's definition of "memory access"Andrew Waterman1-0/+55
2018-11-06Updated status of counters. Not ready for ratification as there are issues o...Krste Asanovic1-3/+3
2018-11-06Stated bytes are 8 bits and using IEC80000-13:2008Krste Asanovic1-1/+2
2018-11-03Removed text regarding big or bi-endian operation. For now, only specifying ...Krste Asanovic1-32/+13
2018-08-26Updated several "user" references to "unprivileged".Krste Asanovic1-1/+1
2018-08-12Minor tweaksAndrew Waterman1-2/+2
2018-08-07Use \geq instead of >=Andrew Waterman1-1/+1
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic1-58/+65
2018-08-05Moved XLEN definition to intro.Krste Asanovic1-8/+11
2018-08-04Updated trap section with feedback from jhauser.Krste Asanovic1-22/+47
2018-07-31Improved/revised interrupt/trap terminology.Krste Asanovic1-72/+85
2018-07-30Adding terminology for categories of traps and interrupts.Krste Asanovic1-22/+57
2018-07-29Clarified difference between interrupts and traps, and behavior ofKrste Asanovic1-7/+13
2018-07-29Big-endian or bi-endian memory systems should notKrste Asanovic1-7/+7
2018-07-29Added more commentary on illegal instruction encodings.Krste Asanovic1-11/+28
2018-07-29Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.Krste Asanovic1-14/+76
2018-07-28Clearing up hart descriptions.Krste Asanovic1-5/+6
2018-07-06Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...Krste Asanovic1-18/+19
2018-06-16Fixed spelling error in intro.tex.Tynan McAuley1-1/+1
2018-05-30ILEN is always a multiple of IALIGNAndrew Waterman1-1/+1
2018-05-30Hyphenate "instruction set" when it's part of a noun phraseAndrew Waterman1-2/+2
2018-02-22Tweak wording of misa.C proposalAndrew Waterman1-1/+2
2018-02-22Introduce IALIGN; propose misa.C semanticsAndrew Waterman1-0/+5
2018-02-09Added clearer definitions of execution environments and harts.Krste Asanovic1-75/+156
2018-01-27Moved commentary on "why new ISA?" to history chapter.Krste Asanovic1-139/+0
2018-01-10Instructions with bits [ILEN-1:0] all ones are illegal (#123)Andrew Waterman1-2/+6
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