riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-05-04	Typos (#379)	Alexandre Joannou	1	-1/+1
2018-12-21	Address space is circular	Andrew Waterman	1	-1/+7
2018-12-20	Clean up naming and define G = IMAFDZicsr_Zifencei	Andrew Waterman	1	-4/+2
2018-11-30	Be more tentative	Andrew Waterman	1	-4/+4
2018-11-30	48+-bit instruction-length encoding scheme is not frozen	Andrew Waterman	1	-11/+19
2018-11-28	Memory section tweaks	Andrew Waterman	1	-2/+2
2018-11-28	Memory section edits	Andrew Waterman	1	-12/+40
2018-11-27	Add Hauser's definition of "memory access"	Andrew Waterman	1	-0/+55
2018-11-06	Updated status of counters. Not ready for ratification as there are issues o...	Krste Asanovic	1	-3/+3
2018-11-06	Stated bytes are 8 bits and using IEC80000-13:2008	Krste Asanovic	1	-1/+2
2018-11-03	Removed text regarding big or bi-endian operation. For now, only specifying ...	Krste Asanovic	1	-32/+13
2018-08-26	Updated several "user" references to "unprivileged".	Krste Asanovic	1	-1/+1
2018-08-12	Minor tweaks	Andrew Waterman	1	-2/+2
2018-08-07	Use \geq instead of >=	Andrew Waterman	1	-1/+1
2018-08-05	Provide new description of misaligned load/store behavior compatible with pri...	Krste Asanovic	1	-58/+65
2018-08-05	Moved XLEN definition to intro.	Krste Asanovic	1	-8/+11
2018-08-04	Updated trap section with feedback from jhauser.	Krste Asanovic	1	-22/+47
2018-07-31	Improved/revised interrupt/trap terminology.	Krste Asanovic	1	-72/+85
2018-07-30	Adding terminology for categories of traps and interrupts.	Krste Asanovic	1	-22/+57
2018-07-29	Clarified difference between interrupts and traps, and behavior of	Krste Asanovic	1	-7/+13
2018-07-29	Big-endian or bi-endian memory systems should not	Krste Asanovic	1	-7/+7
2018-07-29	Added more commentary on illegal instruction encodings.	Krste Asanovic	1	-11/+28
2018-07-29	Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.	Krste Asanovic	1	-14/+76
2018-07-28	Clearing up hart descriptions.	Krste Asanovic	1	-5/+6
2018-07-06	Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...	Krste Asanovic	1	-18/+19
2018-06-16	Fixed spelling error in intro.tex.	Tynan McAuley	1	-1/+1
2018-05-30	ILEN is always a multiple of IALIGN	Andrew Waterman	1	-1/+1
2018-05-30	Hyphenate "instruction set" when it's part of a noun phrase	Andrew Waterman	1	-2/+2
2018-02-22	Tweak wording of misa.C proposal	Andrew Waterman	1	-1/+2
2018-02-22	Introduce IALIGN; propose misa.C semantics	Andrew Waterman	1	-0/+5
2018-02-09	Added clearer definitions of execution environments and harts.	Krste Asanovic	1	-75/+156
2018-01-27	Moved commentary on "why new ISA?" to history chapter.	Krste Asanovic	1	-139/+0
2018-01-10	Instructions with bits [ILEN-1:0] all ones are illegal (#123)	Andrew Waterman	1	-2/+6
2017-12-06	Make explicit that 0xFFFF is an illegal opcode	Andrew Waterman	1	-1/+2
2017-06-12	Use https for link to riscv.org	Paul Wise	1	-1/+1
2017-05-15	Fix some orphaned/widowed commentary sections	Andrew Waterman	1	-2/+2
2017-05-15	Move ILEN definition to introduction	Andrew Waterman	1	-0/+9
2017-05-07	Actioned Robert Watson's feedback.	Krste Asanovic	1	-1/+1
2017-05-03	Reordered chapters to be somewhat more logical.	Krste Asanovic	1	-1/+1
2017-03-20	Clarified that RISC-V uses two's-complement arithmetic for signed integer val...	Krste Asanovic	1	-1/+3
2017-02-01	Reorganize directory structure	Andrew Waterman	1	-0/+502