| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-05-14 | zimm -> uimm in CSR instruction listing | Andrew Waterman | 1 | -3/+3 | |
| This makes the table match the CSR chapter. | |||||
| 2019-03-05 | Add Q opcode listing | Andrew Waterman | 1 | -0/+405 | |
| 2018-11-20 | Fix colliding labels | Andrew Waterman | 1 | -5/+0 | |
| h/t @pmundkur Resolves #278 | |||||
| 2018-11-06 | CSRRx is called Zicsr | Andrew Waterman | 1 | -1/+1 | |
| 2018-11-06 | Separate FENCE.I and CSRRx from RV32I table | Andrew Waterman | 1 | -179/+232 | |
| 2018-08-27 | Move out-of-date vector encoding to V chapter | Andrew Waterman | 1 | -735/+0 | |
| 2018-08-25 | Clarify that FENCE opcode bits aren't required to be 0 | Andrew Waterman | 1 | -7/+5 | |
| (They're reserved for future use) | |||||
| 2018-05-02 | Updates to the memory consistency model spec | Daniel Lustig | 1 | -1/+1 | |
| This giant patch is the result of months of work from a lot of different people in the memory model TG. | |||||
| 2018-03-21 | Add preliminary V encoding | Andrew Waterman | 1 | -0/+735 | |
| 2017-05-07 | SB/UJ -> B/J | Andrew Waterman | 1 | -2/+2 | |
| 2017-04-14 | Fix FMV.X.W/FMV.W.X in instruction listings | Andrew Waterman | 1 | -2/+2 | |
| 2017-02-01 | Reorganize directory structure | Andrew Waterman | 1 | -0/+1958 | |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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