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2020-03-03Clarify operation of 32-bit AMOs on RV64.Krste Asanovic1-1/+2
Closes #465
2019-12-27FENCE.I isn't in the I baseAndrew Waterman1-1/+1
FENCE.I is, of course, not allowed in LR/SC sequences. But we don't need to explicitly exclude it, since it's now in Zifencei, rather than I.
2019-12-13A extension v2.1 has been ratifiedRatified-IMAFDQCAndrew Waterman1-1/+1
2019-10-11Incorporate feedback from Paul DonahueAndrew Waterman1-2/+2
2019-10-06Incorporate Anthony Coulter's feedbackAndrew Waterman1-3/+4
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/6rpIanfXCVc/SIp_dwvCAgAJ
2019-10-02Address some of Derek's feedbacklrscAndrew Waterman1-15/+4
2019-10-02Fix editing error that allowed FENCE.I in LR/SC sequencesAndrew Waterman1-2/+3
2019-10-02Fix typoAndrew Waterman1-1/+1
2019-10-02Incorporate aspects of PR #444Andrew Waterman1-5/+17
h/t Marc
2019-10-02Avoid using "virtual address" in normative text of unprivileged spec (#430)Andrew Waterman1-2/+5
2019-10-02Incorporate some of #416 and #418Andrew Waterman1-17/+57
2019-10-02More LR/SC feedbackAndrew Waterman1-4/+5
2019-10-02Move CAS code figure to the same page it's referenced onAndrew Waterman1-34/+32
2019-10-02Introduce "reservation set" terminologyAndrew Waterman1-44/+53
2019-10-02More Derek feedbackAndrew Waterman1-3/+2
2019-10-02Address Derek's feedbackAndrew Waterman1-23/+29
2019-10-02Constrained loops must use same *virtual* address for SCAndrew Waterman1-2/+2
2019-10-02Incorporate Dan's feedbackAndrew Waterman1-25/+26
2019-10-02More LR/SC updatesAndrew Waterman1-1/+5
2019-10-02Remove page breaksAndrew Waterman1-2/+0
2019-10-02Weaken LR/SC progress guaranteeAndrew Waterman1-49/+106
2019-07-30Use consistent terms for exception typesAndrew Waterman1-4/+4
@jscheid-ventana originally contributed this, but I tweaked the hyphenation. Resolves #422
2019-05-15Correct iteration in LR/SC CAS example. (#384)David-Horner1-2/+3
Address argument was clobbered. Signed-off-by: David Horner <ds2horner@gmail.com>
2019-05-07Clarify the behaviour of LR.W/D and SC.W/DColumbus2401-7/+9
Concerning issue #376.
2019-02-08Clarify behavior of LR.rl and SC.aq (#339)Andrew Waterman1-3/+6
Resolves #338
2019-01-17JALR is not allowed within LR/SC sequencesAndrew Waterman1-1/+1
This used to be the case, until an editing error several years ago.
2018-12-10subset -> extensionAndrew Waterman1-3/+3
2018-11-16Improved wording.Krste Asanovic1-2/+2
2018-11-16Clarified that LR/SC forward progress guarantee might only hold for a subset ↵Krste Asanovic1-3/+5
of instruction and data memory space depending on execution environment.
2018-11-07Describe the AMOs as "bitwise", not "logical" (#259)Palmer Dabbelt1-2/+2
"logical AND" usually means C's "&&" operator, not "&" operator. Thanks to Bodhisattva Debnath for pointing out the issue!
2018-11-06Allow access exceptions to be reported on misaligned atomic memory ↵Krste Asanovic1-10/+18
operations where they should not be emulated.
2018-08-12Removed redundant text that LR can reserve a different subset on each ↵Krste Asanovic1-3/+1
invocation.
2018-08-09Clarified reservation range and that SC only pairs with immediately ↵Krste Asanovic1-20/+25
preceding LR.
2018-08-07Clarified A definitions.Krste Asanovic1-27/+18
2018-08-06Removed obsolete commentary.Krste Asanovic1-11/+0
2018-07-06Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual ↵Andrew Waterman1-1/+1
into tymcauley-misc-fixes
2018-06-18Strengthen guidance on the need to clear a reservation using SC (#198)Alex Bradbury1-2/+3
Commit 170f3c5 clarified that reservations can be cleared with an SC to a dummy memory location. As discussed <https://github.com/riscv/riscv-isa-manual/commit/170f3c52bd134ac90c3467f77925fdaa68e9b8f6#commitcomment-29386537>, this patch makes it clear that the reservation "should" be cleared in this way during a preemptive context switch. Anyone writing preemptive context switch code should be forcibly clearing load reservations. Although other mechanisms might be used, this is the standard way of doing it (hence "should" rather than "must").
2018-06-16Fixed grammar inconsistency in a.tex.Tynan McAuley1-1/+1
Changed "can not" to "cannot". While both are acceptable, "cannot" is used throughout the document.
2018-06-14Fix outdated commentary about LR/SC and context switchingAndrew Waterman1-6/+2
Closes #193
2018-06-11Remove misleading note about AMOSWAP elisionAndrew Waterman1-6/+0
The note implied that it's legal to elide silent stores. This is not true with respect to the consistency model.
2018-05-06Luke's feedbackAndrew Waterman1-1/+1
2018-05-02Updates to the memory consistency model specDaniel Lustig1-56/+48
This giant patch is the result of months of work from a lot of different people in the memory model TG.
2018-03-28Make LR/SC CAS example adhere to the forward-progress constraintsAndrew Waterman1-1/+2
2018-02-07Add commentary about LR/SC forward-progress guaranteeAndrew Waterman1-0/+5
2017-12-12Describe optional support for misaligned AMOs (#117)Andrew Waterman1-9/+28
* Fix typo * Describe misaligned AMOs * Improve commentary for misaligned AMO emulation
2017-10-20Remove privileged architecture detail from user specAndrew Waterman1-3/+11
2017-07-21Fix description of LR/SC for data sizeAndrew Waterman1-3/+4
LR.D/SC.W and LR.W/SC.D aren't guaranteed to succeed.
2017-05-06Updated to define and use hart more consistently.Krste Asanovic1-13/+22
Added warnings about changes to memory model.
2017-04-17Recommend LR for sequentially consistent loadsAndrew Waterman1-6/+6
2017-04-09Fix typoAndrew Waterman1-1/+1
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