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2022-06-22Merge pull request #859 from riscv/zicntr-zihpm-ratificationAndrew Waterman1-52/+86
2022-06-22Restructure commentary sections to move portions close to relevant normative ...Krste Asanovic1-26/+28
2022-06-22Be consistent in use of "pseudoinstruction".Krste Asanovic1-7/+7
2022-06-21Remove inconsistencies in the Zihpm description.Krste Asanovic1-9/+19
2022-06-21Confirm that real-time clock synchronization is a mandate, but also relay in ...Krste Asanovic1-1/+8
2022-06-21Weaken impossible mandate on clock period, and provide some commentary.Krste Asanovic1-3/+8
2022-06-21Make clear that non-canonical CSR reads are also legal for counters.Krste Asanovic1-1/+8
2022-06-21Removed text assuming these were part of a base, and removed explicit referen...Krste Asanovic1-23/+26
2022-06-21Make chapter heading have name of extensions defined therein.Krste Asanovic1-2/+2
2022-06-06Add draft of Zfb extensionAndrew Waterman2-0/+100
2022-06-03Define RVV-RVTSO bindingsAndrew Waterman1-0/+6
2022-06-02Replaced nonstandard with non-standard.Krste Asanovic3-5/+5
2022-05-12Ztso wordsmithingAndrew Waterman1-1/+1
2022-05-02Improve implemented/enabled textAndrew Waterman1-5/+4
2022-05-02Clarify what is meant by "implemented" (#842)John Hauser1-2/+33
2022-04-26Add single-letter "H" extension to the tableTsukasa OI1-1/+2
2022-04-26Remove multi-letter H* extensions from namingTsukasa OI1-15/+0
2022-04-23Delete more nonexistent extensions from the naming constraintsAndrew Waterman1-1/+1
2022-04-23D extension is implied by V extension (#840)Tsukasa #01 (a4lg)1-1/+1
2022-04-23Strict single-letter extensions on Table 28.1 (Standard ISA extension names) ...Tsukasa #01 (a4lg)1-4/+1
2022-04-10Fix typo: "instruction" -> "instructions" (#834)Edward Forgacs1-1/+1
2022-04-04Fix BOOM URLAndrew Waterman1-1/+1
2022-03-28Add note about FCVT.Q.L[U] never rounding (like FCVT.D.W[U])Andrew Waterman1-1/+2
2022-03-18Fix copy-paste errors in Sv57x4 descriptionAndrew Waterman1-4/+4
2022-03-12improve description of store-conditional failure codes (#827)Andrew Waterman1-3/+3
2022-03-01Svpbmt cannot override vacant PMA regions. (#826)Paul Donahue1-0/+2
2022-03-01Update priv spec contributorsAndrew Waterman1-2/+2
2022-02-24Hypervisor: use HFENCE.GVMA after PMP write to synchronize VS-enabled-G-disab...John Ingalls1-8/+5
2022-02-23Improve description of SvnapotAndrew Waterman1-6/+6
2022-02-22Zihintntl: fix chapter label (#821)Antony Pavlov1-1/+1
2022-02-17rocket-chip is hosted at chipsalliance, not freechipsprojectAndrew Waterman1-1/+1
2022-02-17Adds CV32E41P to MARCHID (#818)Ibrahim Abu Kharmeh1-0/+1
2022-02-08Make FP conversion/move section names consistentAndrew Waterman2-2/+2
2022-01-25Update priv preface to reflect draft statusAndrew Waterman1-0/+32
2022-01-25misa.V means "V" vector extensionAndrew Waterman1-1/+1
2022-01-25Remove tentative purpose for reserved misa.B and misa.J bitsAndrew Waterman1-2/+2
2022-01-20Merge pull request #815 from a4lg/update-instr-table-20220121Andrew Waterman2-300/+306
2022-01-21Update Instruction Tables based on riscv-opcodesTsukasa OI2-300/+306
2022-01-19Merge pull request #813 from a4lg/riscv-hints-new-1-20220119Andrew Waterman3-14/+34
2022-01-20Remove "no hints are defined" text in RVCTsukasa OI1-1/+1
2022-01-20Add Zihintntl hints to HINT Instruction tablesTsukasa OI3-8/+28
2022-01-20Change compressed hint exampleTsukasa OI1-2/+2
2022-01-20Replace semicolon with a colonTsukasa OI1-1/+1
2022-01-20Remove "no hints are defined" text in RV64ITsukasa OI1-2/+2
2022-01-15Zihintntl: Fix number of hint instruction variants (#812)Tsukasa #01 (a4lg)1-1/+1
2022-01-14hypervisor: Add Sv57 to &x4 address witdth list (#811)Dylan Reid1-1/+1
2022-01-10Incorporate Kruckemyer's feedback on NTLAndrew Waterman1-6/+6
2022-01-10Clarify forbidden execution scenarios in A.1 litmus test (#809)Daniel Mangum1-1/+1
2022-01-09fix formattingAndrew Waterman1-1/+1
2022-01-09Add Zihintntl spec (#810)Andrew Waterman3-0/+204
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