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AgeCommit message (Expand)AuthorFilesLines
2018-03-26Clarify that SUM does not permit supervisor execution from user pagesAndrew Waterman1-0/+1
2018-03-23Removed some outdated text.Krste Asanovic1-53/+9
2018-03-23Closed issue #150Krste Asanovic1-2/+2
2018-03-21Add preliminary V encodingAndrew Waterman1-0/+735
2018-03-21John Hauser's alternative writable-misa.C proposalAndrew Waterman4-14/+24
2018-03-20Cleaned up configuration sections.Krste Asanovic2-199/+143
2018-03-03Merge pull request #139 from riscv/misa-cAndrew Waterman4-17/+24
2018-03-03Fix bug in RVC opcode mapAndrew Waterman1-1/+1
2018-02-27Added commentary on counter/timers.Krste Asanovic1-1/+64
2018-02-22Fix mepc/sepc definitions w.r.t. IALIGNAndrew Waterman2-11/+4
2018-02-22Tweak wording of misa.C proposalAndrew Waterman2-3/+5
2018-02-22Introduce IALIGN; propose misa.C semanticsAndrew Waterman3-6/+18
2018-02-09Added clearer definitions of execution environments and harts.Krste Asanovic5-117/+183
2018-02-08Clarify description of unused FENCE bitsAndrew Waterman1-4/+4
2018-02-07Add commentary about LR/SC forward-progress guaranteeAndrew Waterman1-0/+5
2018-01-27Moved commentary on "why new ISA?" to history chapter.Krste Asanovic2-139/+140
2018-01-27citation use macro for rev versionKrste Asanovic1-1/+1
2018-01-24Add Steve to acksAndrew Waterman1-1/+2
2018-01-23Added commentary on fixed interrupt priority scheme for mip/mie.Krste Asanovic1-0/+42
2018-01-23Standardized on pseudoinstruction.Krste Asanovic4-20/+20
2018-01-23Clarified when mip/mie bits are hardwired to zero when user mode present.Krste Asanovic3-268/+537
2018-01-23Use y instead of a in PMP addressesAndrew Waterman1-8/+8
2018-01-10Instructions with bits [ILEN-1:0] all ones are illegal (#123)Andrew Waterman1-2/+6
2018-01-03Fix typoAndrew Waterman1-2/+2
2017-12-28WIRI/WPRI fields should be hardwired to 0 (#121)Andrew Waterman1-4/+8
2017-12-27Admit that the V extension existsAndrew Waterman1-2/+2
2017-12-13Fix typoDaniel Lustig1-1/+1
2017-12-12Add memory consistency model draft proposalAndrew Waterman4-401/+373
2017-12-12Add (but don't integrate) memory model chapterAndrew Waterman1-0/+1838
2017-12-12Update historyAndrew Waterman1-3/+15
2017-12-12Fix inconsistency between RVC text and opcode tableAndrew Waterman1-3/+3
2017-12-12Fix typoAndrew Waterman1-1/+1
2017-12-12Describe optional support for misaligned AMOs (#117)Andrew Waterman4-9/+49
2017-12-12DisambiguateAndrew Waterman1-1/+1
2017-12-12hcounteren doesn't existAndrew Waterman1-1/+1
2017-12-11Fix xIE descriptive errorAndrew Waterman3-2/+4
2017-12-06Make explicit that 0xFFFF is an illegal opcodeAndrew Waterman1-1/+2
2017-12-06Constrain all harts to use same A/D-bit management schemeAndrew Waterman2-2/+2
2017-12-06Add commentary that FENCE.I doesn't work for migrated threadsAndrew Waterman1-0/+7
2017-12-03Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic5-5/+42
2017-11-27Add R-type format to priv-instr-tableAndrew Waterman1-0/+10
2017-11-12Clarify WLRL semanticsAndrew Waterman1-1/+1
2017-11-12Mark useless PMP NAPOT case as reservedAndrew Waterman1-0/+1
2017-11-09Make MPP/SPP WARL fieldsAndrew Waterman2-3/+7
2017-11-09State that writable-but-not-readable PMPs are reservedAndrew Waterman1-1/+2
2017-11-09Specify meaning of R/W/X bits in PMPAndrew Waterman1-0/+8
2017-11-09Specify meaning of R/W/X bits in PTEAndrew Waterman1-0/+13
2017-11-09Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic8-22/+1133
2017-11-09Add hypervisor draft proposalAndrew Waterman3-5/+1097
2017-11-09fix typosAndrew Waterman4-8/+8
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