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AgeCommit message (Expand)AuthorFilesLines
2017-04-07Add vectored interruptsAndrew Waterman1-17/+40
2017-04-02Improved rationale for AMO selection.Krste Asanovic2-12/+17
2017-04-02Added rationale for choice of divide overflow results.Krste Asanovic1-0/+8
2017-03-31Incorporate PMP feedbackAndrew Waterman2-3/+6
2017-03-31Commentary on 'mtval' refers to 'mtbadinst' instead of 'mtval'Michael Clark1-1/+1
2017-03-30Update PMP CSR listingAndrew Waterman1-4/+8
2017-03-30Modify PMP encoding and improve descriptionAndrew Waterman1-67/+59
2017-03-30PMP cleanupAndrew Waterman1-6/+8
2017-03-29Clarify that misaligned accesses violating PMPs become partially visibleAndrew Waterman1-3/+11
2017-03-29Fix typoAndrew Waterman1-1/+1
2017-03-29Add PMP to prefaceAndrew Waterman1-0/+1
2017-03-29Improve PMP sectionAndrew Waterman2-45/+241
2017-03-28First draft of PMP specAndrew Waterman1-20/+149
2017-03-28Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...Krste Asanovic3-23/+23
2017-03-28Add preface entry for page fault cause renumberingAndrew Waterman1-0/+4
2017-03-28Separate access faults from VM faultsAndrew Waterman2-24/+62
2017-03-27Added David Horner's suggestion of faster way to test for base ISA width if m...Krste Asanovic1-2/+4
2017-03-26Replaced mbadaddr with mbadbits register, which can now capture badKrste Asanovic4-21/+75
2017-03-24Simplified MXL/SXL/UXL design. Now, no checks for monotonically decreasing X...Krste Asanovic1-36/+53
2017-03-21Added rationale for removal of machine-mode base-and-bounds schemes for now.Krste Asanovic1-2/+9
2017-03-20Small changes.Krste Asanovic1-5/+5
2017-03-20Specify encoding of mvendorid fieldAndrew Waterman1-4/+16
2017-03-20Clarified that RISC-V uses two's-complement arithmetic for signed integer val...Krste Asanovic1-1/+3
2017-03-20Changed mvendorid to hold the JEDEC manufacturer code for the core vendor as ...Krste Asanovic2-8/+14
2017-03-20Now mideleg /medeleg only exist if lower privilege mode exists and can take t...Krste Asanovic2-2/+12
2017-03-20Removed explicit convention on shadow CSRs.Krste Asanovic3-20/+29
2017-03-20Add changelog entries for PUM -> SUM and MXRAndrew Waterman1-0/+3
2017-03-20PUM -> SUM; expose MXR to S-modeAndrew Waterman2-37/+49
2017-03-19fix typoAndrew Waterman1-2/+2
2017-03-19Excised H-mode from spec.Krste Asanovic10-289/+280
2017-03-19Fixed up licence and contributor details on front page.Krste Asanovic2-15/+38
2017-03-18Software shouldn't use misaligned accesses on non-idempotent regionsAndrew Waterman1-0/+7
2017-03-16Simplify interrupt-stack disciplineAndrew Waterman3-9/+7
2017-03-13Add TSR mechanismAndrew Waterman1-6/+21
2017-03-13Fix setvl descriptionAndrew Waterman1-4/+4
2017-03-13C.SLLI takes both rs1 and rd argsAndrew Waterman1-2/+2
2017-03-10Fix quadrant for C.ADD/C.MV/C.EBREAKAndrew Waterman1-3/+3
2017-03-07Update UXL/SXL languageAndrew Waterman1-25/+21
2017-03-07Make some supervisor fields WPRIAndrew Waterman2-20/+79
2017-03-06One liners to correct register designation in rvc-instr-tableDavid Horner1-3/+3
2017-03-06fix typoAndrew Waterman1-1/+1
2017-03-03misa Base => MXLAndrew Waterman2-15/+15
2017-03-01Added placeholder for J extension.Krste Asanovic6-2/+18
2017-02-27Fix typoAndrew Waterman2-2/+3
2017-02-26Add TW bitAndrew Waterman1-12/+24
2017-02-26Incorporate more Hauser feedbackAndrew Waterman3-23/+28
2017-02-26Expand PPN to 44 bits in Sv39/Sv48 PTEsAndrew Waterman1-15/+15
2017-02-26SX -> SXLAndrew Waterman2-25/+25
2017-02-25Expand sptbr.MODE field; don't spec Sv57/Sv64 for nowAndrew Waterman1-285/+23
2017-02-25Add Paolo to acknowledgementsAndrew Waterman1-1/+1
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