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2017-05-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic4-16/+26
2017-05-05Remove option to hardwire UXL/SXL to 0Andrew Waterman2-14/+17
2017-05-05PPN LSBs must be clear for superpage PTEsAndrew Waterman1-1/+6
2017-05-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic1-3/+4
2017-05-05Remove redundant clause in SFENCE.VMA descriptionAndrew Waterman1-3/+1
2017-05-04Reserve D/A/U bitsAndrew Waterman1-0/+3
2017-05-03Moved chapters into canonical extension listing order.Krste Asanovic3-3/+3
2017-05-03Added note indicating that the P extension might be reworkedKrste Asanovic2-0/+12
2017-05-03Reordered chapters to be somewhat more logical.Krste Asanovic3-6/+7
2017-05-03Clarified result of REM*W on divide by zero.Krste Asanovic1-15/+18
2017-05-03Changed front page of spec to follow move to Creative Commons License.Krste Asanovic2-10/+34
2017-05-02Clarify commentaryAndrew Waterman1-1/+1
2017-05-02Incorporate Anthony Coulter's feedbackAndrew Waterman2-10/+25
2017-04-27Improve ECALL textAndrew Waterman1-1/+1
2017-04-27Describe ECALL/EBREAK operation in privileged architectureAndrew Waterman2-1/+74
2017-04-25Clean up JALR hint textAndrew Waterman2-7/+9
2017-04-24Modified behavior of JALR hint bits to better support macro-op fusion of LUI;...Krste Asanovic3-9/+53
2017-04-20Make mcause table easier to understandAndrew Waterman1-6/+6
2017-04-20Improve stval/mtval warl textAndrew Waterman2-10/+16
2017-04-17Recommend LR for sequentially consistent loadsAndrew Waterman1-6/+6
2017-04-17mepc, sepc, mtval, and stval are WARLAndrew Waterman2-0/+20
2017-04-16Define the behavior of FMA(inf, 0, qNaN)Andrew Waterman2-0/+9
2017-04-16Formatting fixesAndrew Waterman1-5/+5
2017-04-14Fix FMV.X.W/FMV.W.X in instruction listingsAndrew Waterman1-2/+2
2017-04-13Renamed FMV.X.S/S.X to FMV.X.W/W.X to be more consistent with load/store inst...Krste Asanovic4-17/+29
2017-04-13Clarified transfers out of f registers and conversion instructions.Krste Asanovic1-1/+10
2017-04-13Added the NaN-boxing scheme for narrower floating-point values held in wider ...Krste Asanovic4-38/+97
2017-04-11stval is optionally written with bad instruction, as with mtvalAndrew Waterman1-0/+14
2017-04-11mtval/stval are zeroed for other exceptionsAndrew Waterman2-3/+6
2017-04-11Clarify [s/m][epc/tval/cause] are only written on exceptions into that modeAndrew Waterman2-17/+41
2017-04-11SPTBR -> SATPAndrew Waterman4-33/+35
2017-04-10Make immediate signs explicit in RVC tableAndrew Waterman2-56/+56
2017-04-10Clarify WFI w.r.t. interrupt delegationAndrew Waterman1-4/+5
2017-04-09Fix typoAndrew Waterman1-1/+1
2017-04-09Fix typoAndrew Waterman1-1/+1
2017-04-07Reserve LSBs of stvec.Andrew Waterman1-3/+5
2017-04-07Add vectored interruptsAndrew Waterman1-17/+40
2017-04-02Improved rationale for AMO selection.Krste Asanovic2-12/+17
2017-04-02Added rationale for choice of divide overflow results.Krste Asanovic1-0/+8
2017-03-31Incorporate PMP feedbackAndrew Waterman2-3/+6
2017-03-31Commentary on 'mtval' refers to 'mtbadinst' instead of 'mtval'Michael Clark1-1/+1
2017-03-30Update PMP CSR listingAndrew Waterman1-4/+8
2017-03-30Modify PMP encoding and improve descriptionAndrew Waterman1-67/+59
2017-03-30PMP cleanupAndrew Waterman1-6/+8
2017-03-29Clarify that misaligned accesses violating PMPs become partially visibleAndrew Waterman1-3/+11
2017-03-29Fix typoAndrew Waterman1-1/+1
2017-03-29Add PMP to prefaceAndrew Waterman1-0/+1
2017-03-29Improve PMP sectionAndrew Waterman2-45/+241
2017-03-28First draft of PMP specAndrew Waterman1-20/+149
2017-03-28Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...Krste Asanovic3-23/+23