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2021-03-15Add FENCE.TSO and PAUSE to RV32I instruction tableAndrew Waterman1-0/+22
2021-03-14Clarify that AMOs use the original address when rd == rs1 (#632)Jessica Clarke1-1/+1
2021-03-05fix typo in prefaceAndrew Waterman1-1/+1
2021-02-23s/NSE/Custom/ in RVC specAndrew Waterman2-4/+4
2021-02-11wrap long lineAndrew Waterman1-1/+3
2021-02-11Merge pull request #398 from riscv/pauseAndrew Waterman5-14/+102
2021-02-10Update prefaceAndrew Waterman1-0/+2
2021-02-10Clarify type of timer interrupt (#617)Bartek Gąsiorzewski1-1/+1
2021-02-10Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778Andrew Waterman1-1/+1
2021-01-14Delete duplicate (and now inconsistent) version number given in body text.Krste Asanovic1-2/+1
2021-01-13Revert "should -> shall in definition of 0 instruction"Andrew Waterman1-1/+1
2021-01-13should -> shall in definition of 0 instructionAndrew Waterman1-1/+1
2021-01-13Explain rationale for seting xPP=U on an xRETAndrew Waterman1-1/+7
2021-01-13Add preface note that N extension was moved to its own chapterAndrew Waterman1-0/+1
2021-01-13Clean up NMI/mepc wordingAndrew Waterman1-2/+2
2021-01-12Additional FS clarificationAndrew Waterman1-1/+1
2021-01-12Clarify rm field on widening conversions (#619)Paul Donahue1-2/+4
2021-01-12spell checkAndrew Waterman1-1/+1
2021-01-12clarify that FS need only be set to dirty if the state is actually changedAndrew Waterman1-0/+4
2021-01-08LR/SC extension commentary tweakAndrew Waterman1-1/+1
2020-12-28Clarify when FP conversions raise the Inexact flagAndrew Waterman1-3/+3
2020-12-28Use consistent wording for FP exception textAndrew Waterman1-1/+1
2020-12-22Make unused misa fields 0 (WARL) rather than WLRL. (#615)Paul Donahue1-1/+1
2020-12-16Further improve HINT text w.r.t. FENCE HINTsAndrew Waterman1-7/+18
2020-12-15Explicitly state rd=0/rs1=0 constraint on PAUSEAndrew Waterman1-1/+1
2020-12-15Improve non-normative text re: multiple PAUSEsAndrew Waterman1-3/+6
2020-12-15Add FENCE with fm=0, pred or succ=0, and rs1/rd != 0 to HINT tableAndrew Waterman2-9/+30
2020-11-19Dedicated section for machine-level memory-mapped registers (not standard CSR...Alexandre Joannou1-114/+116
2020-11-17Clarify G bits in all G-stage PTEs are reserved (#613)gfavor1-0/+3
2020-11-06PMP uses physical addresses (not effective addresses) (#610)Paul Donahue1-2/+2
2020-11-06Update editorsAndrew Waterman1-2/+2
2020-10-29Update contributorsAndrew Waterman1-1/+2
2020-10-27mcounteren is WARLAndrew Waterman1-0/+4
2020-10-25PMP TOR clarificationsAndrew Waterman1-1/+8
2020-10-18Another attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-17Attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-17Update HINT table to indicate PAUSE HINT allocationAndrew Waterman1-3/+7
2020-10-17Indicate that PAUSE uses fm=0Andrew Waterman1-1/+2
2020-10-17Clarify expected ballpark for Pause duration (#604)gfavor1-0/+1
2020-10-17Update zihintpause.texgfavor1-8/+7
2020-10-17Add rationale for PAUSE vs. MONITOR/MWAITAndrew Waterman1-0/+8
2020-10-17Add note about PAUSE and LR/SC forward progressAndrew Waterman1-0/+3
2020-10-17Add PAUSE instructionAndrew Waterman4-3/+40
2020-10-17fm=0 for FENCE HINTsAndrew Waterman1-1/+2
2020-10-13Both HWBPs and EBREAKs populate mtval (#601)Andrew Waterman2-3/+4
2020-10-12marchid request for NEORV32 core (#579)pause-public-review-20201013Stephan1-0/+1
2020-10-06For emphasis, make MXR/SUM commentary normativeAndrew Waterman1-2/+0
2020-10-02Disabling H extension does not ensure illegal instruction traps (#595)John Hauser1-4/+2
2020-10-01Fix build with some versions of pdflatexAndrew Waterman1-1/+1
2020-09-30Disabling and reenabling extensions makes their state unspecified (#585)Andrew Waterman1-0/+4
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