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AgeCommit message (Expand)AuthorFilesLines
2019-10-02More LR/SC feedbackAndrew Waterman1-4/+5
2019-10-02Move CAS code figure to the same page it's referenced onAndrew Waterman1-34/+32
2019-10-02Introduce "reservation set" terminologyAndrew Waterman1-44/+53
2019-10-02More Derek feedbackAndrew Waterman1-3/+2
2019-10-02Address Derek's feedbackAndrew Waterman1-23/+29
2019-10-02Constrained loops must use same *virtual* address for SCAndrew Waterman1-2/+2
2019-10-02Clarify that LR/SC reservation granule mustn't cross page boundariesAndrew Waterman1-3/+3
2019-10-02Incorporate Dan's feedbackAndrew Waterman2-27/+28
2019-10-02More LR/SC updatesAndrew Waterman3-1/+11
2019-10-02Remove page breaksAndrew Waterman1-2/+0
2019-10-02Weaken LR/SC progress guaranteeAndrew Waterman2-53/+110
2019-10-02Clarify that pmpcfg.L takes effect even when pmpcfg.A=0Andrew Waterman1-0/+4
2019-09-28Improve supervisor interrupt control sectionAndrew Waterman1-41/+119
2019-09-28Fix editing error in Atomicity PMA figure captionAndrew Waterman1-2/+1
2019-09-28Update prefaceAndrew Waterman1-0/+1
2019-09-27Improve interrupt-delegation descriptionAndrew Waterman1-116/+163
2019-09-27Add mcause section labelAndrew Waterman1-0/+1
2019-09-27Permit hardwiring of some mideleg bits to 1Andrew Waterman1-2/+13
2019-09-25Refine xepc/xtval WARL requirementsAndrew Waterman2-8/+16
2019-09-13Make PMP description consistent with MPRV descriptionAndrew Waterman1-4/+6
2019-09-12Mark misa.G as reserved until the discovery mechansim is definedAndrew Waterman1-9/+1
2019-09-10marchid for c-class core of SHAKTI (#448)Neel Gala1-0/+1
2019-09-06Remove outdated commentaryAndrew Waterman1-1/+1
2019-08-30mstatus TVM, TW, and TSR are WARL fieldsAndrew Waterman1-4/+6
2019-08-29Fix outcome description for Figure A.15Andrew Waterman1-1/+1
2019-08-27Closes #359.Krste Asanovic1-1/+2
2019-08-27Like page-table walks, main memory might not support i-fetchAndrew Waterman1-2/+10
2019-08-27Main memory support atomics is a platform mandate, not an ISA oneAndrew Waterman1-3/+8
2019-08-27scause must be able to hold the values 0-31Andrew Waterman2-2/+5
2019-08-26Page-table walks are distinct access types for PMA purposesAndrew Waterman1-0/+9
2019-08-26Update contributorsAndrew Waterman1-1/+1
2019-08-26Remove released PDFsAndrew Waterman8-0/+0
2019-08-26Add link to archiveAndrew Waterman1-3/+6
2019-08-26Relaxed I/O adheres to Appendix A 4.2archiveAndrew Waterman2-9/+12
2019-08-21Merge pull request #441 from Columbus240/I440Andrew Waterman1-46/+46
2019-08-21Define Upper-Half User-Level Timer CSRs for RV32I (#439)Columbus2401-5/+10
2019-08-21Use RV32 consistently in the CSR listingColumbus2401-12/+12
2019-08-21Remove trailing whitespace from priv-csrs.texColumbus2401-34/+34
2019-08-20Fix typo in hcounteren privilegeAndrew Waterman1-1/+1
2019-08-16hypervisor: add performance counter delta registersPaolo Bonzini2-0/+52
2019-08-16Remove pre-PMP-standardization textAndrew Waterman1-2/+2
2019-07-30Use consistent terms for exception typesAndrew Waterman4-28/+28
2019-07-26Add @marceg to contributorsAndrew Waterman1-2/+3
2019-07-26The execution environment must guarantee harts make progressAndrew Waterman1-0/+17
2019-07-23Fix extension ordering in naming chapter and prefaceAndrew Waterman2-6/+7
2019-07-21Move N extension into its own chapter in the priv specAndrew Waterman9-371/+356
2019-07-18More hypervisor updates courtesy of @jhauser-usAndrew Waterman1-91/+282
2019-07-18Fix poor figure placementAndrew Waterman1-2/+3
2019-07-12Update SweRV project URL (#408)Thomas Wicki1-1/+1
2019-07-12Improve description of mtimecmp code sequenceAndrew Waterman1-1/+3
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