Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2019-06-21 | add BlackParrot and BaseJump Manycore (#396) | black-parrot | 1 | -0/+2 | |
2019-06-21 | Fix preface style | Andrew Waterman | 1 | -2/+2 | |
2019-06-21 | Merge pull request #395 from riscv/endianness | Andrew Waterman | 4 | -38/+215 | |
Add endianness control proposal to priv spec | |||||
2019-06-21 | Add mstatush to preface | Andrew Waterman | 1 | -0/+2 | |
2019-06-21 | Need SFENCE after change to SBE | Andrew Waterman | 1 | -0/+3 | |
2019-06-21 | Spelling | Andrew Waterman | 2 | -2/+2 | |
2019-06-21 | Bi-endian systems reset as little-endian | Andrew Waterman | 1 | -0/+2 | |
2019-06-21 | Add commentary | Andrew Waterman | 1 | -0/+9 | |
2019-06-19 | Add endianness control proposal to priv spec | Andrew Waterman | 4 | -37/+198 | |
Contributed by @jhauser-us | |||||
2019-06-16 | Bump priv spec to v1.12-draft | Andrew Waterman | 2 | -6/+40 | |
2019-06-16 | Hypervisor v0.4 draft | Andrew Waterman | 3 | -314/+379 | |
Courtesy @jhauser-us | |||||
2019-06-08 | Added text to indicate this is the ratified 1.11 version of the spec.Ratified-IMFDQC-and-Priv-v1.11 | Krste Asanovic | 2 | -6/+7 | |
2019-06-08 | Updated preface to indicate this is now ratified spec. | Krste Asanovic | 2 | -19/+19 | |
2019-05-31 | Merge pull request #391 from imphil/counter-enable-typo | Krste Asanovic | 1 | -1/+1 | |
Tiny editorial fix | |||||
2019-05-31 | Tiny editorial fix | Philipp Wagner | 1 | -1/+1 | |
2019-05-21 | Adding FENCE to the table of RV64 HINT instructions (#387) | Luís Marques | 1 | -1/+2 | |
2019-05-15 | Correct iteration in LR/SC CAS example. (#384) | David-Horner | 1 | -2/+3 | |
Address argument was clobbered. Signed-off-by: David Horner <ds2horner@gmail.com> | |||||
2019-05-14 | zimm -> uimm in CSR instruction listing | Andrew Waterman | 1 | -3/+3 | |
This makes the table match the CSR chapter. | |||||
2019-05-09 | Clarify reserved/HINT encodings in C chapter text (#382) | Andrew Waterman | 1 | -21/+54 | |
This PR essentially copies the information from the encoding table at the end of the chapter into the mainline text. The intent is to remove any doubt about what happens when an instruction's operand constraints are not met. | |||||
2019-05-07 | Merge branch 'Columbus240-ClarifyLRSC' | Andrew Waterman | 1 | -7/+9 | |
2019-05-07 | Clarify the behaviour of LR.W/D and SC.W/D | Columbus240 | 1 | -7/+9 | |
Concerning issue #376. | |||||
2019-05-06 | Add note about FLE vs. BGE inconsistency | Andrew Waterman | 1 | -0/+7 | |
2019-05-04 | Typos (#379) | Alexandre Joannou | 2 | -2/+2 | |
* Fix typo ">" to "$>$" * typo of -> on | |||||
2019-04-23 | Update contributors | Andrew Waterman | 1 | -1/+1 | |
cc @kdockser | |||||
2019-04-20 | Merge pull request #373 from riscv/hellwig-sbi | Krste Asanovic | 2 | -33/+24 | |
Don't reference the SBI in normative privileged spec sections | |||||
2019-04-20 | Express stvec alignment constraint more clearly | Andrew Waterman | 1 | -5/+4 | |
2019-04-19 | Don't reference the SBI in normative privileged spec sections | Andrew Waterman | 2 | -33/+24 | |
Submitted on behalf of Christoph Hellwig For context, see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/kL-2LhgUmcE/xxySlYT0CQAJ | |||||
2019-04-19 | Clarify hypervisor/PLIC sentiment | Andrew Waterman | 1 | -4/+8 | |
2019-04-19 | Remove outdated clause indicating incorrect exception priorities | Andrew Waterman | 1 | -3/+4 | |
The clause was superseded by Table 3.7, but we failed to delete it. Closes #372 | |||||
2019-04-18 | Fix erroneous caption | Andrew Waterman | 1 | -1/+1 | |
Resolves #371 | |||||
2019-04-17 | Merge branch 'pdonahue-ventana-ligature' | Andrew Waterman | 2 | -0/+8 | |
2019-04-17 | Finesse ligatures to work with Adobe Acrobat Reader search and cut-and-paste | Paul Donahue | 2 | -0/+8 | |
2019-04-15 | Update CSR access ordering section to clarify ordering is two-sided | Andrew Waterman | 1 | -8/+10 | |
This is just a clarification, as it follows from the accesses being performed in program order. | |||||
2019-04-11 | clarify in commentary that environment break == EBREAK | Andrew Waterman | 1 | -1/+1 | |
2019-04-11 | Explain when sideleg/sedeleg must exist | Andrew Waterman | 1 | -0/+6 | |
Closes #366 | |||||
2019-04-11 | forgot to bump hypervisor spec draft version | Andrew Waterman | 1 | -1/+1 | |
2019-04-08 | Elucidate two uses of the word "error" | Andrew Waterman | 2 | -2/+4 | |
Resolves #365 | |||||
2019-04-05 | Version 20190405-Priv-MSU-Ratification for ratification votePriv-MSU-Ratification-20190405 | Andrew Waterman | 1 | -2/+2 | |
2019-04-05 | Privileged Spec: Add dscratch0/1 to CSR listing (#361) | Philipp Wagner | 1 | -1/+2 | |
dscratch1 was missing from the listing, dscratch0 was named only dscratch. | |||||
2019-04-05 | mtime is a read-write register | Andrew Waterman | 1 | -1/+1 | |
Closes #362 | |||||
2019-03-28 | mhpmcounters are WARL | Andrew Waterman | 1 | -1/+7 | |
We inadvertently excised commentary that mentioned this possibility in 8e52ffa49d09437c69fec6e173dfbddeb9e8ea1a. Thanks to @ccelio for pointing this out. | |||||
2019-03-26 | Add preface entry for mcountinhibit CSR | Andrew Waterman | 1 | -0/+2 | |
Resolves #358 | |||||
2019-03-26 | Minor grammar fix (#357) | pdonahue-ventana | 1 | -1/+1 | |
2019-03-25 | Change "pc" to "address" for clarity | Andrew Waterman | 2 | -6/+7 | |
Resolves #356 | |||||
2019-03-24 | Improve CSR ordering section | Andrew Waterman | 3 | -32/+47 | |
h/t David Kruckemyer | |||||
2019-03-21 | Revoke old access token and use env variable going forward | Andrew Waterman | 1 | -1/+1 | |
2019-03-15 | Add more MXR/SUM commentary | Andrew Waterman | 1 | -0/+6 | |
2019-03-14 | memory -> main memory | Andrew Waterman | 1 | -1/+1 | |
2019-03-13 | Fix HFENCE definitions to include all stores, not just local ones | Andrew Waterman | 1 | -7/+7 | |
2019-03-13 | Improve synchronous exception priority table/description | Andrew Waterman | 1 | -18/+19 | |