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2018-08-06Added comment that we might consider different pattern for RV128 to improve c...Krste Asanovic1-0/+7
2018-08-06Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignme...Rishiyur S. Nikhil1-1/+1
2018-08-06Clarified FENCE.TSO under base implementation.Krste Asanovic1-5/+17
2018-08-06Fix Typo: Recover a lost brace in assembly.tex (#219)Columbus2401-1/+1
2018-08-06Fix typo in syntactic-dependence tableAndrew Waterman1-1/+1
2018-08-06Cleaned up RV64 chapter to remove platform-specific mandates.Krste Asanovic2-8/+18
2018-08-06CSR instructions file.Krste Asanovic1-0/+277
2018-08-06Cleaned up RV32E to remove platform-specific mandates.Krste Asanovic1-40/+14
2018-08-06Moved CSR instructions into separate chapter.Krste Asanovic4-355/+111
2018-08-05Provide new description of misaligned load/store behavior compatible with pri...Krste Asanovic3-82/+122
2018-08-05Minor cleanups and clarifications.Krste Asanovic1-34/+44
2018-08-05update preface.Krste Asanovic1-1/+2
2018-08-05Moved XLEN definition to intro.Krste Asanovic2-11/+12
2018-08-04Updated trap section with feedback from jhauser.Krste Asanovic1-22/+47
2018-08-02Minor change to the operational memory model (#216)Shaked Flur1-1/+2
2018-07-31Improved/revised interrupt/trap terminology.Krste Asanovic1-72/+85
2018-07-30Adding terminology for categories of traps and interrupts.Krste Asanovic1-22/+57
2018-07-30clarificationKrste Asanovic1-1/+1
2018-07-29Minor clarifications.Krste Asanovic1-11/+13
2018-07-29Clarified that AUIPC uses PC of AUIPC instruction itself.Krste Asanovic1-10/+12
2018-07-29Clarified difference between interrupts and traps, and behavior ofKrste Asanovic1-7/+13
2018-07-29Big-endian or bi-endian memory systems should notKrste Asanovic1-7/+7
2018-07-29Added more commentary on illegal instruction encodings.Krste Asanovic1-11/+28
2018-07-29Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.Krste Asanovic2-14/+86
2018-07-28Clearing up hart descriptions.Krste Asanovic1-5/+6
2018-07-28Added commentary on why there are no RV32 moves to and from double-precision ...Krste Asanovic1-0/+22
2018-07-27Put note to point to current draft of V standard.Krste Asanovic1-0/+3
2018-07-16Updates to HINT sections.Krste Asanovic2-18/+26
2018-07-15More work on HINTsAndrew Waterman3-24/+121
2018-07-15Fix spelling of "pseudoinstruction"Andrew Waterman3-9/+9
2018-07-15Add section on RV32I HINTsAndrew Waterman1-0/+63
2018-07-15Reverting what would have been unintended change in spec. InterruptsKrste Asanovic1-12/+14
2018-07-13Clarified description of interrupt enables across multiple privilege modes.Krste Asanovic1-8/+19
2018-07-12Add commentary that we favor zero-extension unless SW demands otherwiseAndrew Waterman1-0/+10
2018-07-11Clarify the behavior of M-mode hardware performance counters.Krste Asanovic1-7/+10
2018-07-09Make JALR assembly format consistent with binutils (#209)Andrew Waterman3-9/+9
2018-07-06Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic2-6/+13
2018-07-06C extension is no longer a draft proposal.Krste Asanovic1-1/+1
2018-07-06Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)Alexandre Joannou2-6/+13
2018-07-06Remove sbi.tex from the root directory. (#211)Atish Patra1-77/+0
2018-07-06Two more small bits of memory model commentary. (#210)Daniel Lustig1-6/+10
2018-07-06Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...Krste Asanovic3-22/+28
2018-07-06Explain how addressing works when UXLEN < SXLENAndrew Waterman1-0/+5
2018-07-06Merge branch 'tymcauley-misc-fixes'Andrew Waterman6-7/+7
2018-07-06Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual in...Andrew Waterman6-7/+7
2018-07-05Merge branch 'daniellustig-memory_model_clarifications_070518'Andrew Waterman5-116/+134
2018-07-05FST -> FSDAndrew Waterman2-3/+3
2018-07-05Version the appendices.Daniel Lustig1-5/+9
2018-07-05FLD and FST are not atomic unless XLEN>=64Daniel Lustig2-3/+6
2018-07-05Small updates to the Ztso specDaniel Lustig1-7/+11
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