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riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
dev/beeman/smctr-ssctr
fix-adoc-IDs
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
wfmi
zam
zfb
ztso-ratification
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2018-08-06
Added comment that we might consider different pattern for RV128 to improve c...
Krste Asanovic
1
-0
/
+7
2018-08-06
Clarified wording in last sentence of Priv Spec section 3.1.12 (mtvec alignme...
Rishiyur S. Nikhil
1
-1
/
+1
2018-08-06
Clarified FENCE.TSO under base implementation.
Krste Asanovic
1
-5
/
+17
2018-08-06
Fix Typo: Recover a lost brace in assembly.tex (#219)
Columbus240
1
-1
/
+1
2018-08-06
Fix typo in syntactic-dependence table
Andrew Waterman
1
-1
/
+1
2018-08-06
Cleaned up RV64 chapter to remove platform-specific mandates.
Krste Asanovic
2
-8
/
+18
2018-08-06
CSR instructions file.
Krste Asanovic
1
-0
/
+277
2018-08-06
Cleaned up RV32E to remove platform-specific mandates.
Krste Asanovic
1
-40
/
+14
2018-08-06
Moved CSR instructions into separate chapter.
Krste Asanovic
4
-355
/
+111
2018-08-05
Provide new description of misaligned load/store behavior compatible with pri...
Krste Asanovic
3
-82
/
+122
2018-08-05
Minor cleanups and clarifications.
Krste Asanovic
1
-34
/
+44
2018-08-05
update preface.
Krste Asanovic
1
-1
/
+2
2018-08-05
Moved XLEN definition to intro.
Krste Asanovic
2
-11
/
+12
2018-08-04
Updated trap section with feedback from jhauser.
Krste Asanovic
1
-22
/
+47
2018-08-02
Minor change to the operational memory model (#216)
Shaked Flur
1
-1
/
+2
2018-07-31
Improved/revised interrupt/trap terminology.
Krste Asanovic
1
-72
/
+85
2018-07-30
Adding terminology for categories of traps and interrupts.
Krste Asanovic
1
-22
/
+57
2018-07-30
clarification
Krste Asanovic
1
-1
/
+1
2018-07-29
Minor clarifications.
Krste Asanovic
1
-11
/
+13
2018-07-29
Clarified that AUIPC uses PC of AUIPC instruction itself.
Krste Asanovic
1
-10
/
+12
2018-07-29
Clarified difference between interrupts and traps, and behavior of
Krste Asanovic
1
-7
/
+13
2018-07-29
Big-endian or bi-endian memory systems should not
Krste Asanovic
1
-7
/
+7
2018-07-29
Added more commentary on illegal instruction encodings.
Krste Asanovic
1
-11
/
+28
2018-07-29
Provide explanation for multiple base ISAs, and ADD/ADDW discrepancy.
Krste Asanovic
2
-14
/
+86
2018-07-28
Clearing up hart descriptions.
Krste Asanovic
1
-5
/
+6
2018-07-28
Added commentary on why there are no RV32 moves to and from double-precision ...
Krste Asanovic
1
-0
/
+22
2018-07-27
Put note to point to current draft of V standard.
Krste Asanovic
1
-0
/
+3
2018-07-16
Updates to HINT sections.
Krste Asanovic
2
-18
/
+26
2018-07-15
More work on HINTs
Andrew Waterman
3
-24
/
+121
2018-07-15
Fix spelling of "pseudoinstruction"
Andrew Waterman
3
-9
/
+9
2018-07-15
Add section on RV32I HINTs
Andrew Waterman
1
-0
/
+63
2018-07-15
Reverting what would have been unintended change in spec. Interrupts
Krste Asanovic
1
-12
/
+14
2018-07-13
Clarified description of interrupt enables across multiple privilege modes.
Krste Asanovic
1
-8
/
+19
2018-07-12
Add commentary that we favor zero-extension unless SW demands otherwise
Andrew Waterman
1
-0
/
+10
2018-07-11
Clarify the behavior of M-mode hardware performance counters.
Krste Asanovic
1
-7
/
+10
2018-07-09
Make JALR assembly format consistent with binutils (#209)
Andrew Waterman
3
-9
/
+9
2018-07-06
Merge branch 'master' of github.com:riscv/riscv-isa-manual
Krste Asanovic
2
-6
/
+13
2018-07-06
C extension is no longer a draft proposal.
Krste Asanovic
1
-1
/
+1
2018-07-06
Help the reader by pointing at TVM, TW and TSR in the relevant sections (#194)
Alexandre Joannou
2
-6
/
+13
2018-07-06
Remove sbi.tex from the root directory. (#211)
Atish Patra
1
-77
/
+0
2018-07-06
Two more small bits of memory model commentary. (#210)
Daniel Lustig
1
-6
/
+10
2018-07-06
Changes to intro as part of rationalizing ISA into ISA-only versus platform-m...
Krste Asanovic
3
-22
/
+28
2018-07-06
Explain how addressing works when UXLEN < SXLEN
Andrew Waterman
1
-0
/
+5
2018-07-06
Merge branch 'tymcauley-misc-fixes'
Andrew Waterman
6
-7
/
+7
2018-07-06
Merge branch 'misc-fixes' of https://github.com/tymcauley/riscv-isa-manual in...
Andrew Waterman
6
-7
/
+7
2018-07-05
Merge branch 'daniellustig-memory_model_clarifications_070518'
Andrew Waterman
5
-116
/
+134
2018-07-05
FST -> FSD
Andrew Waterman
2
-3
/
+3
2018-07-05
Version the appendices.
Daniel Lustig
1
-5
/
+9
2018-07-05
FLD and FST are not atomic unless XLEN>=64
Daniel Lustig
2
-3
/
+6
2018-07-05
Small updates to the Ztso spec
Daniel Lustig
1
-7
/
+11
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