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2019-05-14zimm -> uimm in CSR instruction listingAndrew Waterman1-3/+3
This makes the table match the CSR chapter.
2019-05-09Clarify reserved/HINT encodings in C chapter text (#382)Andrew Waterman1-21/+54
This PR essentially copies the information from the encoding table at the end of the chapter into the mainline text. The intent is to remove any doubt about what happens when an instruction's operand constraints are not met.
2019-05-07Merge branch 'Columbus240-ClarifyLRSC'Andrew Waterman1-7/+9
2019-05-07Clarify the behaviour of LR.W/D and SC.W/DColumbus2401-7/+9
Concerning issue #376.
2019-05-06Add note about FLE vs. BGE inconsistencyAndrew Waterman1-0/+7
2019-05-04Typos (#379)Alexandre Joannou2-2/+2
* Fix typo ">" to "$>$" * typo of -> on
2019-04-23Update contributorsAndrew Waterman1-1/+1
cc @kdockser
2019-04-20Merge pull request #373 from riscv/hellwig-sbiKrste Asanovic2-33/+24
Don't reference the SBI in normative privileged spec sections
2019-04-20Express stvec alignment constraint more clearlyAndrew Waterman1-5/+4
2019-04-19Don't reference the SBI in normative privileged spec sectionsAndrew Waterman2-33/+24
Submitted on behalf of Christoph Hellwig For context, see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/kL-2LhgUmcE/xxySlYT0CQAJ
2019-04-19Clarify hypervisor/PLIC sentimentAndrew Waterman1-4/+8
2019-04-19Remove outdated clause indicating incorrect exception prioritiesAndrew Waterman1-3/+4
The clause was superseded by Table 3.7, but we failed to delete it. Closes #372
2019-04-18Fix erroneous captionAndrew Waterman1-1/+1
Resolves #371
2019-04-17Merge branch 'pdonahue-ventana-ligature'Andrew Waterman2-0/+8
2019-04-17Finesse ligatures to work with Adobe Acrobat Reader search and cut-and-pastePaul Donahue2-0/+8
2019-04-15Update CSR access ordering section to clarify ordering is two-sidedAndrew Waterman1-8/+10
This is just a clarification, as it follows from the accesses being performed in program order.
2019-04-11clarify in commentary that environment break == EBREAKAndrew Waterman1-1/+1
2019-04-11Explain when sideleg/sedeleg must existAndrew Waterman1-0/+6
Closes #366
2019-04-11forgot to bump hypervisor spec draft versionAndrew Waterman1-1/+1
2019-04-08Elucidate two uses of the word "error"Andrew Waterman2-2/+4
Resolves #365
2019-04-05Version 20190405-Priv-MSU-Ratification for ratification votePriv-MSU-Ratification-20190405Andrew Waterman1-2/+2
2019-04-05Privileged Spec: Add dscratch0/1 to CSR listing (#361)Philipp Wagner1-1/+2
dscratch1 was missing from the listing, dscratch0 was named only dscratch.
2019-04-05mtime is a read-write registerAndrew Waterman1-1/+1
Closes #362
2019-03-28mhpmcounters are WARLAndrew Waterman1-1/+7
We inadvertently excised commentary that mentioned this possibility in 8e52ffa49d09437c69fec6e173dfbddeb9e8ea1a. Thanks to @ccelio for pointing this out.
2019-03-26Add preface entry for mcountinhibit CSRAndrew Waterman1-0/+2
Resolves #358
2019-03-26Minor grammar fix (#357)pdonahue-ventana1-1/+1
2019-03-25Change "pc" to "address" for clarityAndrew Waterman2-6/+7
Resolves #356
2019-03-24Improve CSR ordering sectionAndrew Waterman3-32/+47
h/t David Kruckemyer
2019-03-21Revoke old access token and use env variable going forwardAndrew Waterman1-1/+1
2019-03-15Add more MXR/SUM commentaryAndrew Waterman1-0/+6
2019-03-14memory -> main memoryAndrew Waterman1-1/+1
2019-03-13Fix HFENCE definitions to include all stores, not just local onesAndrew Waterman1-7/+7
2019-03-13Improve synchronous exception priority table/descriptionAndrew Waterman1-18/+19
2019-03-13Improve commentary on CSR orderingAndrew Waterman1-5/+8
2019-03-13Improve wording of satp/ASID/caching/speculation paragraphAndrew Waterman1-5/+16
@dkruckemyer-ventana This isn't meant to encode any semantic changes, just to clarify the existing text. But I thought you might want to read over it.
2019-03-13Revise CSR-ordering sectionAndrew Waterman1-6/+22
2019-03-13Clarify which exception is raised in two casesAndrew Waterman1-2/+2
Closes #354
2019-03-12Specify synchronous exception priority orderingAndrew Waterman2-0/+47
Closes #327
2019-03-12Clarify that CSR accesses can be ordered with FENCEsAndrew Waterman1-0/+17
2019-03-12Reformat CSR address map tableAndrew Waterman1-29/+39
Closes #293
2019-03-08SFENCE.VMA orders visible stores, not just local storesAndrew Waterman1-5/+5
2019-03-08Clarify misleading text in Zifencei chapterAndrew Waterman1-5/+5
As the instruction's definition states, it orders stores that are visible with subsequent fetches. By definition, this includes a subset of other hart's stores. Yet, some other text may lend the impression to the reader that it only orders the current hart's stores.
2019-03-07Update prefaceAndrew Waterman1-0/+1
2019-03-07Update mcause/scause tables to allocate some custom exception causesAndrew Waterman2-12/+22
2019-03-07Add software constraint for future global-ASID extensionAndrew Waterman3-3/+23
Closes #348
2019-03-07Tweaks suggested by Bill HuffmanAndrew Waterman4-4/+4
2019-03-07Restate FENCE.TSO constraints from Table 2.1 in the textAndrew Waterman1-1/+3
2019-03-07SFENCE.VMA clarificationsAndrew Waterman1-3/+8
- It orders implicit references to the page tables, not all implicit references - It is a hart-local operation
2019-03-05Hypervisor draft v0.3Andrew Waterman1-62/+90
2019-03-05Embellish descriptions in Q chapterAndrew Waterman1-4/+10
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