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2021-06-02Merge branch 'virtual-memory' into SvnapotDaniel Lustig26-288/+838
2021-06-02Merge branch 'master' into virtual-memoryDaniel Lustig26-241/+813
2021-06-02Remove the "C" bit, per virt mem TG voteDaniel Lustig2-47/+23
2021-05-31Merge pull request #652 from rafaelcalcada/masterAndrew Waterman1-0/+1
2021-06-01Steel Core marchid addedRafael Calcada1-0/+1
2021-05-25Use plural "base ISAs" rather than "base ISA" when appropriateAndrew Waterman7-17/+18
2021-05-25Fix capitalization of HINTsAndrew Waterman1-1/+1
2021-05-23Fix hyphenationAndrew Waterman4-11/+11
2021-05-20Clarify need for HFENCE.GVMA after hgatp.MODE changeAndrew Waterman1-0/+5
2021-05-18Assin version number 0.1 to ZmmulAndrew Waterman1-1/+1
2021-05-17Fix typoDaniel Lustig1-1/+1
2021-05-17Typo and clarificationDaniel Lustig1-3/+4
2021-05-17Merge pull request #648 from riscv/zmmulKrste Asanovic1-0/+20
2021-05-17Incorporate Krste's feedbackAndrew Waterman1-8/+0
2021-05-15Add Zmmul section to M chapterAndrew Waterman1-0/+28
2021-05-03Merge pull request #645 from riscv/listofitemsAndrew Waterman2-0/+401
2021-05-03Add missing style fileAndrew Waterman2-0/+401
2021-05-03Merge pull request #644 from EwoutH/patch-1Andrew Waterman1-2/+1
2021-05-03Travis CI: Remove deprecated 'sudo' keyEwout ter Hoeven1-1/+0
2021-05-03Travis CI: Update build environment to Ubuntu 20.04 FocalEwout ter Hoeven1-1/+1
2021-05-01marchid request for RudolV (#643)Jörg Mische1-0/+1
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock2-63/+62
2021-04-23Resolve inconsistency regarding C and N bitsDaniel Lustig1-13/+12
2021-04-23Merge branch 'virtual-memory' into SvnapotDaniel Lustig2-22/+36
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman2-1/+3
2021-04-13Requesting marchid for cv32e40x and cv32e40s (#630)Arjan Bink1-0/+2
2021-04-13marchid request for Ibex (#638)Greg Chadwick1-0/+1
2021-04-02Define canonical location of K extension in ISA stringAndrew Waterman1-1/+2
2021-03-24Clarify hypervisor privilege hierarchy/global interrupt enablesAndrew Waterman1-0/+8
2021-03-15Add FENCE.TSO and PAUSE to RV32I instruction tableAndrew Waterman1-0/+22
2021-03-14Clarify that AMOs use the original address when rd == rs1 (#632)Jessica Clarke1-1/+1
2021-03-08Clarify PA zero-extension rulesDaniel Lustig1-2/+14
2021-03-05fix typo in prefaceAndrew Waterman1-1/+1
2021-03-03Reserved PTE encodings also trigger page faultsDaniel Lustig1-3/+3
2021-03-03Fix formatting of preface bulletDaniel Lustig1-6/+6
2021-03-03Reserved PTE bits cause page faultsDaniel Lustig2-7/+7
2021-02-24Reword over-SFENCE'ing commentaryDaniel Lustig1-4/+7
2021-02-23s/NSE/Custom/ in RVC specAndrew Waterman2-4/+4
2021-02-23Reword text about SFENCE.VMA with invalid VADaniel Lustig1-8/+7
2021-02-21Add Svnapot Extension v0.1Daniel Lustig2-23/+177
2021-02-21Add Sv57 and Sv57x4 in the expected wayDaniel Lustig3-26/+202
2021-02-21Remove Svnapot from this branchDaniel Lustig2-185/+20
2021-02-21SFENCE.VMA with invalid rs1 has no effect.Daniel Lustig1-0/+8
2021-02-11wrap long lineAndrew Waterman1-1/+3
2021-02-11Merge pull request #398 from riscv/pauseAndrew Waterman5-14/+102
2021-02-10Update prefaceAndrew Waterman1-0/+2
2021-02-10Clarify type of timer interrupt (#617)Bartek Gąsiorzewski1-1/+1
2021-02-10Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778Andrew Waterman1-1/+1
2021-02-08Recommend tight sequences of SFENCE.VMAsDaniel Lustig1-0/+32
2021-02-02Rename Zsn to SvnapotDaniel Lustig2-12/+12
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