diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/m.tex | 33 |
1 files changed, 18 insertions, 15 deletions
@@ -93,21 +93,14 @@ cannot be the same as {\em rs1} or {\em rs2}). Microarchitectures can then fuse these into a single divide operation instead of performing two separate divides. -DIVW and DIVUW instructions are only valid for RV64, and divide the -lower 32 bits of {\em rs1} by the lower 32 bits of {\em rs2}, treating -them as signed and unsigned integers respectively, placing the 32-bit -quotient in {\em rd}, sign-extended to 64 bits. REMW and REMUW -instructions are only valid for RV64, and provide the corresponding -signed and unsigned remainder operations respectively. Both REMW and -REMUW sign-extend the 32-bit result to 64 bits. - -The semantics for division by zero and division overflow are summarized in -Table~\ref{tab:divby0}. The quotient of division by zero has all bits set, -i.e. $2^{XLEN}-1$ for unsigned division or $-1$ for signed division. The -remainder of division by zero equals the dividend. Signed division overflow -occurs only when the most-negative integer, $-2^{XLEN-1}$, is divided by $-1$. -The quotient of signed division overflow is equal to the dividend, and the -remainder is zero. Unsigned division overflow cannot occur. +The semantics for division by zero and division overflow are +summarized in Table~\ref{tab:divby0}. The quotient of division by +zero has all bits set, i.e. $2^{XLEN}-1$ for unsigned division or $-1$ +for signed division. The remainder of division by zero equals the +dividend. Signed division overflow occurs only when the most-negative +integer, $-2^{XLEN-1}$, is divided by $-1$. The quotient of signed +division overflow is equal to the dividend, and the remainder is zero. +Unsigned division overflow cannot occur. \vspace{0.1in} \begin{table}[h] @@ -145,3 +138,13 @@ unsigned divider implementations. Signed division is often implemented using an unsigned division circuit and specifying the same overflow result simplifies the hardware. \end{commentary} + +DIVW and DIVUW instructions are only valid for RV64, and divide the +lower 32 bits of {\em rs1} by the lower 32 bits of {\em rs2}, treating +them as signed and unsigned integers respectively, placing the 32-bit +quotient in {\em rd}, sign-extended to 64 bits. REMW and REMUW +instructions are only valid for RV64, and provide the corresponding +signed and unsigned remainder operations respectively. Both REMW and +REMUW always sign-extend the 32-bit result to 64 bits, including on a +divide by zero. + |