diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/c.tex | 2 | ||||
| -rw-r--r-- | src/gmaps.tex | 4 | ||||
| -rw-r--r-- | src/history.tex | 4 | ||||
| -rw-r--r-- | src/intro.tex | 4 | ||||
| -rw-r--r-- | src/naming.tex | 2 | ||||
| -rw-r--r-- | src/preface.tex | 4 | ||||
| -rw-r--r-- | src/priv-insns.tex | 2 | ||||
| -rw-r--r-- | src/rv32.tex | 4 | ||||
| -rw-r--r-- | src/rv32e.tex | 2 | ||||
| -rw-r--r-- | src/sbi.tex | 2 | ||||
| -rw-r--r-- | src/v.tex | 2 |
11 files changed, 16 insertions, 16 deletions
@@ -3,7 +3,7 @@ \label{compressed} This chapter describes the current draft proposal for the RISC-V -standard compressed instruction set extension, named ``C'', which +standard compressed instruction-set extension, named ``C'', which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. The C extension can be added to any of the base ISAs (RV32, RV64, RV128), and we use the diff --git a/src/gmaps.tex b/src/gmaps.tex index 2caaa79..a00ce65 100644 --- a/src/gmaps.tex +++ b/src/gmaps.tex @@ -12,7 +12,7 @@ opcode maps and instruction-set listings for RV32G and RV64G. Table~\ref{opcodemap} shows a map of the major opcodes for RVG. Major opcodes with 3 or more lower bits set are reserved for instruction lengths greater than 32 bits. Opcodes marked as {\em reserved} should -be avoided for custom instruction set extensions as they might be used +be avoided for custom instruction-set extensions as they might be used by future standard extensions. Major opcodes marked as {\em custom-0} and {\em custom-1} will be avoided by future standard extensions and are recommended for use by custom instruction-set extensions within @@ -29,7 +29,7 @@ be added (forming RV32GC and RV64GC) to improve performance, code size, and energy efficiency, though with some additional hardware complexity. -As we move beyond IMAFDC into further instruction set extensions, the +As we move beyond IMAFDC into further instruction-set extensions, the added instructions tend to be more domain-specific and only provide benefits to a restricted class of applications, e.g., for multimedia or security. Unlike most commercial ISAs, the RISC-V ISA design diff --git a/src/history.tex b/src/history.tex index 8e6713d..0e6e816 100644 --- a/src/history.tex +++ b/src/history.tex @@ -104,7 +104,7 @@ disadvantages: Our position is that the ISA is perhaps the most important interface in a computing system, and there is no reason that such an important interface should be proprietary. The dominant commercial ISAs are -based on instruction set concepts that were already well known over 30 +based on instruction-set concepts that were already well known over 30 years ago. Software developers should be able to target an open standard hardware target, and commercial processor designers should compete on implementation quality. @@ -143,7 +143,7 @@ projects using RISC-V. \section{History from Revision 1.0 of ISA manual} -The RISC-V ISA and instruction set manual builds upon several earlier +The RISC-V ISA and instruction-set manual builds upon several earlier projects. Several aspects of the supervisor-level machine and the overall format of the manual date back to the T0 (Torrent-0) vector microprocessor project at UC Berkeley and ICSI, begun in 1992. T0 was diff --git a/src/intro.tex b/src/intro.tex index d9e1f57..884c30b 100644 --- a/src/intro.tex +++ b/src/intro.tex @@ -1,6 +1,6 @@ \chapter{Introduction} -RISC-V (pronounced ``risk-five'') is a new instruction set +RISC-V (pronounced ``risk-five'') is a new instruction-set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will also become a standard free and open architecture for industry @@ -83,7 +83,7 @@ instruction fetch unit. A RISC-V-compatible core might support multiple RISC-V-compatible hardware threads, or {\em harts}, through multithreading. -A RISC-V core might have additional specialized instruction set +A RISC-V core might have additional specialized instruction-set extensions or an added {\em coprocessor}. We use the term {\em coprocessor} to refer to a unit that is attached to a RISC-V core and is mostly sequenced by a RISC-V instruction stream, but which diff --git a/src/naming.tex b/src/naming.tex index 04dca0d..2fac80a 100644 --- a/src/naming.tex +++ b/src/naming.tex @@ -31,7 +31,7 @@ extensions to the integer bases are: ``A'' for atomic memory instructions, ``F'' for single-precision floating-point instructions, and ``D'' for double-precision floating-point instructions. -Any RISC-V instruction set variant can be succinctly described by +Any RISC-V instruction-set variant can be succinctly described by concatenating the base integer prefix with the names of the included extensions. For example, ``RV64IMAFD''. diff --git a/src/preface.tex b/src/preface.tex index 88981a0..b63507b 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -46,7 +46,7 @@ The major changes in this version of the document include: \parskip 0pt \itemsep 1pt \item Added clearer and more precise definitions of execution environments and harts. -\item Defined instruction set categories: {\em standard}, {\em +\item Defined instruction-set categories: {\em standard}, {\em reserved}, {\em custom}, {\em non-standard}, and {\em non-conforming}. \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, and changed their behavior on signaling-NaN inputs to conform to the @@ -128,7 +128,7 @@ The major changes in this version of the document include: \item Added note indicating that the P extension might be reworked into an integer packed-SIMD proposal for fixed-point operations using the integer registers. -\item A draft proposal of the V vector instruction set extension. +\item A draft proposal of the V vector instruction-set extension. \item An early draft proposal of the N user-level traps extension. \item An expanded pseudoinstruction listing. \item Removal of the calling convention chapter, which has been superseded by diff --git a/src/priv-insns.tex b/src/priv-insns.tex index e1c388c..d3ac22a 100644 --- a/src/priv-insns.tex +++ b/src/priv-insns.tex @@ -1,6 +1,6 @@ \chapter{RISC-V Privileged Instruction Set Listings} -This chapter presents instruction set listings for all instructions +This chapter presents instruction-set listings for all instructions defined in the RISC-V Privileged Architecture. \input{priv-instr-table} diff --git a/src/rv32.tex b/src/rv32.tex index 8b386c1..0ab911c 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -413,7 +413,7 @@ register-register instructions. No integer computational instructions cause arithmetic exceptions. \begin{commentary} -We did not include special instruction set support for overflow checks +We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches. Overflow checking for unsigned addition requires only a single @@ -754,7 +754,7 @@ boundary. \begin{commentary} Instruction fetch misaligned exceptions are not possible on machines that support extensions with 16-bit aligned instructions, such as the -compressed instruction set extension, C. +compressed instruction-set extension, C. \end{commentary} Return-address prediction stacks are a common feature of diff --git a/src/rv32e.tex b/src/rv32e.tex index fa1ef53..2c08be5 100644 --- a/src/rv32e.tex +++ b/src/rv32e.tex @@ -40,7 +40,7 @@ Systems with hardware floating-point must use an I base. \section{RV32E Instruction Set} -RV32E uses the same instruction set encoding as RV32I, except that use +RV32E uses the same instruction-set encoding as RV32I, except that use of register specifiers {\tt x16}--{\tt x31} in an instruction will result in an illegal instruction exception being raised. diff --git a/src/sbi.tex b/src/sbi.tex index ea42aff..5f13002 100644 --- a/src/sbi.tex +++ b/src/sbi.tex @@ -26,7 +26,7 @@ RISC-V, including: \item The presence and version of supported instruction-set extensions is obtained via an SBI call to return the configuration string rather than a machine register. This allows for an arbitrarily - large definition of instruction set extensions, and simplifies + large definition of instruction-set extensions, and simplifies virtualization where the returned machine configuration might be modified to emulate different architectures on a given hardware platform. @@ -2,7 +2,7 @@ \label{sec:bits} This chapter presents a proposal for the RISC-V base vector -instruction set extension. The base vector extension is intended to +instruction-set extension. The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains. |