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Diffstat (limited to 'src')
| -rw-r--r-- | src/machine.tex | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index ca8f7a1..5d0d60e 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1528,6 +1528,10 @@ to memory-mapped control registers, which are used by remote harts to provide machine-level interprocessor interrupts. A hart can write its own MSIP bit using the same memory-mapped control register. +If a system has only one hart, or if a platform standard supports the +delivery of machine-level interprocessor interrupts through external +interrupts (MEI) instead, then {\tt mip}.MSIP and {\tt mie}.MSIE may +both be hardwired to zeros. If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of {\tt mip} and SEIE, STIE, and SSIE of {\tt mie} are hardwired to zeros. |