31 files changed, 38 insertions, 38 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index 9fae7ab..ad6652b 100644
--- a/src/a-st-ext.adoc
+++ b/src/a-st-ext.adoc
@@ -1,5 +1,5 @@
 [[atomics]]
-== "A" Standard Extension for Atomic Instructions, Version 2.1
+== "A" Extension for Atomic Instructions, Version 2.1
 
 The standard atomic-instruction extension, named "A", contains
 instructions that atomically read-modify-write memory to support
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
index 18680dd..21cded7 100644
--- a/src/b-st-ext.adoc
+++ b/src/b-st-ext.adoc
@@ -1,5 +1,5 @@
 [[bits]]
-== "B" Standard Extension for Bit Manipulation, Version 1.0.0
+== "B" Extension for Bit Manipulation, Version 1.0.0
 
 The B standard extension comprises instructions provided by the Zba, Zbb, and
 Zbs extensions.
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index 71536c4..b4fe138 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -1,5 +1,5 @@
 [[compressed]]
-== "C" Standard Extension for Compressed Instructions, Version 2.0
+== "C" Extension for Compressed Instructions, Version 2.0
 
 This chapter describes the RISC-V standard compressed instruction-set
 extension, named "C", which reduces static and dynamic code size by
diff --git a/src/cmo.adoc b/src/cmo.adoc
index c477dca..08dde4b 100644
--- a/src/cmo.adoc
+++ b/src/cmo.adoc
@@ -1,5 +1,5 @@
 [[cmo]]
-== Base Cache Management Operation ISA Extensions
+== Extensions for Base Cache Management Operation ISA
 
 === Pseudocode for instruction semantics
 
diff --git a/src/counters.adoc b/src/counters.adoc
index cf646c6..f4a34af 100644
--- a/src/counters.adoc
+++ b/src/counters.adoc
@@ -1,5 +1,5 @@
 [[counters]]
-== "Zicntr" and "Zihpm" Counters, Version 2.0
+== "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
 
 RISC-V ISAs provide a set of up to thirty-two 64-bit performance
 counters and timers that are accessible via unprivileged XLEN-bit
@@ -7,7 +7,7 @@ read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits
 are accessed via CSR registers `0xC80`–`0xC9F`). These counters are
 divided between the "Zicntr" and "Zihpm" extensions.
 
-=== "Zicntr" Standard Extension for Base Counters and Timers
+=== "Zicntr" Extension for Base Counters and Timers
 
 The Zicntr standard extension comprises the first three of these
 counters (CYCLE, TIME, and INSTRET), which have dedicated functions
@@ -173,7 +173,7 @@ reading its upper and lower halves.
         bne          x3, x4, again
 
 
-=== "Zihpm" Standard Extension for Hardware Performance Counters
+=== "Zihpm" Extension for Hardware Performance Counters
 
 The Zihpm extension comprises up to 29 additional unprivileged 64-bit
 hardware performance counters, `hpmcounter3-hpmcounter31`. When
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc
index 17629dd..7c5eb4c 100644
--- a/src/d-st-ext.adoc
+++ b/src/d-st-ext.adoc
@@ -1,4 +1,4 @@
-== "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
+== "D" Extension for Double-Precision Floating-Point, Version 2.2
 
 This chapter describes the standard double-precision floating-point
 instruction-set extension, which is named "D" and adds
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc
index 24941ed..96d5b44 100644
--- a/src/f-st-ext.adoc
+++ b/src/f-st-ext.adoc
@@ -1,7 +1,7 @@
 :stem: latexmath
 
 [[single-float]]
-== "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
+== "F" Extension for Single-Precision Floating-Point, Version 2.2
 
 This chapter describes the standard instruction-set extension for
 single-precision floating-point, which is named "F" and adds
diff --git a/src/j-st-ext.adoc b/src/j-st-ext.adoc
index 836e899..68c1d0d 100644
--- a/src/j-st-ext.adoc
+++ b/src/j-st-ext.adoc
@@ -1,5 +1,5 @@
 [[j-extendj]]
-==  "J" Standard Extension for Dynamically Translated Languages, Version 0.0
+==  "J"  Extension for Dynamically Translated Languages, Version 0.0
 
 This chapter is a placeholder for a future standard extension to support
 dynamically translated languages.
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc
index ac1d70b..5f3c7de 100644
--- a/src/m-st-ext.adoc
+++ b/src/m-st-ext.adoc
@@ -1,5 +1,5 @@
 [[mstandard]]
-== "M" Standard Extension for Integer Multiplication and Division, Version 2.0
+== "M" Extension for Integer Multiplication and Division, Version 2.0
 
 This chapter describes the standard integer multiplication and division
 instruction extension, which is named "M" and contains instructions
diff --git a/src/p-st-ext.adoc b/src/p-st-ext.adoc
index f5013ee..fabd30b 100644
--- a/src/p-st-ext.adoc
+++ b/src/p-st-ext.adoc
@@ -1,5 +1,5 @@
 [[packedsimd]]
-== "P" Standard Extension for Packed-SIMD Instructions, Version 0.2
+== "P" Extension for Packed-SIMD Instructions, Version 0.2
 [NOTE]
 ====
 Discussions at the 5th RISC-V workshop indicated a desire to drop this
diff --git a/src/q-st-ext.adoc b/src/q-st-ext.adoc
index 50978c6..3940ea7 100644
--- a/src/q-st-ext.adoc
+++ b/src/q-st-ext.adoc
@@ -1,4 +1,4 @@
-== "Q" Standard Extension for Quad-Precision Floating-Point, Version 2.2
+== "Q" Extension for Quad-Precision Floating-Point, Version 2.2
 
 This chapter describes the Q standard extension for 128-bit
 quad-precision binary floating-point instructions compliant with the
diff --git a/src/rnmi.adoc b/src/rnmi.adoc
index f505f56..24b5e66 100644
--- a/src/rnmi.adoc
+++ b/src/rnmi.adoc
@@ -1,5 +1,5 @@
 [[rnmi]]
-== "Smrnmi" Standard Extension for Resumable Non-Maskable Interrupts, Version 0.5
+== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 0.5
 
 [WARNING]
 ====
diff --git a/src/scalar-crypto.adoc b/src/scalar-crypto.adoc
index 82a1fd0..1e8a6df 100644
--- a/src/scalar-crypto.adoc
+++ b/src/scalar-crypto.adoc
@@ -1,4 +1,4 @@
-== Cryptography Extensions Volume I: Scalar & Entropy Source Instructions, Version 1.0.1
+== Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
 
 === Changelog
 
diff --git a/src/smepmp.adoc b/src/smepmp.adoc
index 547f723..44142d4 100644
--- a/src/smepmp.adoc
+++ b/src/smepmp.adoc
@@ -1,5 +1,5 @@
 [[smepmp]]
-== PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)
+== "Smepmp" Enhancements for memory access and execution prevention on Machine mode
 === Introduction
 
 Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.
diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc
index 3ee5aae..b19f491 100644
--- a/src/sscofpmf.adoc
+++ b/src/sscofpmf.adoc
@@ -1,5 +1,5 @@
 [[Sscofpmf]]
-== "Sscofpmf" Count Overflow and Mode-Based Filtering Extension, Version 1.0.0
+== "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0.0
 
 The current Privileged specification defines mhpmevent CSRs to select and
 control event counting by the associated hpmcounter CSRs, but provides no
diff --git a/src/sstc.adoc b/src/sstc.adoc
index bbee9a9..078cc50 100644
--- a/src/sstc.adoc
+++ b/src/sstc.adoc
@@ -1,5 +1,5 @@
 [[Sstc]]
-== Sstc Standard Extension for Supervisor-mode Timer Interrupts, Version 1.0.0
+== "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0.0
 
 The current Privileged arch specification only defines a hardware mechanism for
 generating machine-mode timer interrupts (based on the mtime and mtimecmp
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index fee8ca7..eb1a45a 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -1670,7 +1670,7 @@ in <<sv32algorithm>>, except LEVELS equals 5 and
 PTESIZE equals 8.
 
 [[svnapot]]
-== "Svnapot" Standard Extension for NAPOT Translation Contiguity, Version 1.0
+== "Svnapot" Extension for NAPOT Translation Contiguity, Version 1.0
 
 In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a
 translation that is part of a range of contiguous virtual-to-physical
@@ -1836,7 +1836,7 @@ first step.
 ====
 
 [[svpbmt]]
-== "Svpbmt" Standard Extension for Page-Based Memory Types, Version 1.0
+== "Svpbmt" Extension for Page-Based Memory Types, Version 1.0
 
 In Sv39, Sv48, and Sv57, bits 62-61 of a leaf page table entry indicate
 the use of page-based memory types that override the PMA(s) for the
@@ -1962,7 +1962,7 @@ attributes used by accesses to the page in question. Otherwise, the
 intermediate attributes are used as the final set of attributes.
 
 [[svinval]]
-== "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
+== "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
 
 The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA
 instructions into finer-grained invalidation and ordering operations
@@ -2054,7 +2054,7 @@ instructions as no-ops.
 ====
 
 [[sec:svadu]]
-== "Svadu" Standard Extension for Hardware Updating of A/D Bits, Version 1.0
+== "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0
 
 The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits.
 
@@ -2069,7 +2069,7 @@ exceptions when A/D bits need be set, instead takes effect.
 The Svade extension is also defined in <<translation>>.
 
 [[sec:svvptc]]
-== "Svvptc" Standard Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
+== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
 
 When the Svvptc extension is implemented, explicit stores that update the Valid
 bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will
@@ -2095,7 +2095,7 @@ fence instructions outweighs the occasional cost of a gratuitous page-fault.
 ====
 
 [[sec:ssqosid]]
-== "Ssqosid" Standard Extension for Quality-of-Service (QoS) Identifiers, Version 1.0
+== "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0
 
 Quality of Service (QoS) is defined as the minimal end-to-end performance
 guaranteed in advance by a service level agreement (SLA) to a workload.
diff --git a/src/vector-crypto.adoc b/src/vector-crypto.adoc
index 788575f..e4ddba0 100644
--- a/src/vector-crypto.adoc
+++ b/src/vector-crypto.adoc
@@ -1,4 +1,4 @@
-== Cryptography Extensions Volume II: Vector Instructions, Version 1.0.0
+== Cryptography Extensions: Vector Instructions, Version 1.0.0
 
 This document describes the Vector Cryptography extensions to the 
 RISC-V Instruction Set Architecture.
diff --git a/src/zacas.adoc b/src/zacas.adoc
index ebb7942..fc3d32f 100644
--- a/src/zacas.adoc
+++ b/src/zacas.adoc
@@ -1,4 +1,4 @@
-== Atomic Compare-and-Swap (CAS) instructions (Zacas), Version 1.0.0
+== "Cas" and "Zacas" Extensions for Atomic Compare-and-Swap Instructions, Version 1.0.0
 
 === Introduction
 
diff --git a/src/zawrs.adoc b/src/zawrs.adoc
index eb94036..398a328 100644
--- a/src/zawrs.adoc
+++ b/src/zawrs.adoc
@@ -1,4 +1,4 @@
-== "Zawrs" Standard extension for Wait-on-Reservation-Set instructions, Version 1.01
+== "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
 
 The Zawrs extension defines a pair of instructions to be used in polling loops 
 that allows a core to enter a low-power state and wait on a store to a memory 
diff --git a/src/zc.adoc b/src/zc.adoc
index 2f2ef37..28135c2 100644
--- a/src/zc.adoc
+++ b/src/zc.adoc
@@ -1,5 +1,5 @@
 [#Zc]
-== "Zc*" Standard Extension for Code Size Reduction
+== "Zc*" Extension for Code Size Reduction
 
 === Zc* Overview
 
diff --git a/src/zfa.adoc b/src/zfa.adoc
index 6c58dbd..942aeef 100644
--- a/src/zfa.adoc
+++ b/src/zfa.adoc
@@ -1,5 +1,5 @@
 [[zfa]]
-== "Zfa" Standard Extension for Additional Floating-Point Instructions, Version 1.0
+== "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0
 
 This chapter describes the Zfa standard extension, which adds
 instructions for immediate loads, IEEE 754-2019 minimum and maximum
diff --git a/src/zfh.adoc b/src/zfh.adoc
index 9e8710e..ab30e3d 100644
--- a/src/zfh.adoc
+++ b/src/zfh.adoc
@@ -1,4 +1,4 @@
-== "Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point, Version 1.0
+== "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0
 
 This chapter describes the Zfh standard extension for 16-bit
 half-precision binary floating-point instructions compliant with the
diff --git a/src/zfinx.adoc b/src/zfinx.adoc
index 718f124..035222d 100644
--- a/src/zfinx.adoc
+++ b/src/zfinx.adoc
@@ -1,5 +1,5 @@
 [[sec:zfinx]]
-== "Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers, Version 1.0
+== "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0
 
 This chapter defines the "Zfinx" extension (pronounced "z-f-in-x")
 that provides instructions similar to those in the standard
diff --git a/src/zicond.adoc b/src/zicond.adoc
index d7bc78e..c909092 100644
--- a/src/zicond.adoc
+++ b/src/zicond.adoc
@@ -1,5 +1,5 @@
 [[Zicond]]
-== "Zicond" Integer Conditional operations extension
+== "Zicond" Extension for Integer Conditional Operations
 
 [[intro]]
 === Introduction
diff --git a/src/zicsr.adoc b/src/zicsr.adoc
index 50183a8..f5096c2 100644
--- a/src/zicsr.adoc
+++ b/src/zicsr.adoc
@@ -1,5 +1,5 @@
 [[csrinsts]]
-== "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
+== "Zicsr", Extension for Control and Status Register (CSR) Instructions, Version 2.0
 
 RISC-V defines a separate address space of 4096 Control and Status
 registers associated with each hart. This chapter defines the full set
diff --git a/src/zifencei.adoc b/src/zifencei.adoc
index a824b49..666effb 100644
--- a/src/zifencei.adoc
+++ b/src/zifencei.adoc
@@ -1,5 +1,5 @@
 [[zifencei]]
-== "Zifencei" Instruction-Fetch Fence, Version 2.0
+== "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
 This chapter defines the "Zifencei" extension, which includes the
 FENCE.I instruction that provides explicit synchronization between
 writes to instruction memory and instruction fetches on the same hart.
diff --git a/src/zihintntl.adoc b/src/zihintntl.adoc
index f855943..8e225cb 100644
--- a/src/zihintntl.adoc
+++ b/src/zihintntl.adoc
@@ -1,5 +1,5 @@
 [[chap:zihintntl]]
-== "Zihintntl" Non-Temporal Locality Hints, Version 1.0
+== "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0
 
 The NTL instructions are HINTs that indicate that the explicit memory
 accesses of the immediately subsequent instruction (henceforth "target
diff --git a/src/zihintpause.adoc b/src/zihintpause.adoc
index e0f1df6..9df71f3 100644
--- a/src/zihintpause.adoc
+++ b/src/zihintpause.adoc
@@ -1,5 +1,5 @@
 [[zihintpause]]
-== "Zihintpause" Pause Hint, Version 2.0
+== "Zihintpause" Extension for Pause Hint, Version 2.0
 The PAUSE instruction is a HINT that indicates the current hart's rate
 of instruction retirement should be temporarily reduced or paused. The
 duration of its effect must be bounded and may be zero.
diff --git a/src/zimop.adoc b/src/zimop.adoc
index b3a8a2e..ab88a4a 100644
--- a/src/zimop.adoc
+++ b/src/zimop.adoc
@@ -1,5 +1,5 @@
 [[zimop]]
-== "Zimop" May-Be-Operations Extension, Version 1.0
+== "Zimop" Extension for May-Be-Operations, Version 1.0
 
 This chapter defines the "Zimop" extension, which introduces the concept of
 instructions that _may be operations_ (MOPs).  MOPs are initially defined to
diff --git a/src/ztso-st-ext.adoc b/src/ztso-st-ext.adoc
index 087295e..f2ce6d1 100644
--- a/src/ztso-st-ext.adoc
+++ b/src/ztso-st-ext.adoc
@@ -1,5 +1,5 @@
 [[ztso]]
-== "Ztso" Standard Extension for Total Store Ordering, Version 1.0 
+== "Ztso" Extension for Total Store Ordering, Version 1.0 
 
 This chapter defines the "Ztso" extension for the RISC-V Total Store
 Ordering (RVTSO) memory consistency model. RVTSO is defined as a delta