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@@ -5,7 +5,7 @@ This chapter describes the Q standard extension for 128-bit quad-precision binar
floating-point instructions compliant with the IEEE 754-2008
arithmetic standard. The quad-precision binary
floating-point instruction-set extension is named ``Q'', and requires
-RV64IFDZicsr. The floating-point registers are now extended to hold either
+RV64IFD. The floating-point registers are now extended to hold either
a single, double, or quad-precision floating-point value (FLEN=128).
The NaN-boxing scheme described in Section~\ref{nanboxing} is now
extended recursively to allow a single-precision value to be NaN-boxed