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Diffstat (limited to 'src/preface.tex')
| -rw-r--r-- | src/preface.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/preface.tex b/src/preface.tex index 73be621..da7bc09 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -41,14 +41,15 @@ The major changes in this version of the document include: \parskip 0pt \itemsep 1pt \item Improvements to the description and commentary. -\item Clarified behavior of FSGNJ.D instruction on single-precision inputs. +\item Clarification of constraints on load-reserved/store-conditional sequences. \item Clarified purpose and behavior of high-order bits of {\tt fcsr}. \item Corrected the description of the FNMADD.{\em fmt} and FNMSUB.{\em fmt} instructions, which had suggested the incorrect sign of a zero result. +\item Specified behavior of narrower (<FLEN) floating-point values held in + wider {\tt f} registers using NaN-boxing model. \item A draft proposal of the V vector instruction set extension. \item An expanded pseudoinstruction listing. \item A new table of control and status register (CSR) mappings. -\item Clarification of constraints on load-reserved/store-conditional sequences. \item Removal of the calling convention chapter, which has been superseded by the RISC-V ELF psABI Specification~\cite{riscv-elf-psabi}. \end{itemize} |