aboutsummaryrefslogtreecommitdiff
path: root/src/machine.tex
diff options
context:
space:
mode:
Diffstat (limited to 'src/machine.tex')
-rw-r--r--src/machine.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex
index 0a7a14c..9960a4c 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1570,8 +1570,8 @@ n}}, respectively. The {\tt time} CSR is a read-only shadow of the
memory-mapped {\tt mtime} register.
\begin{commentary}
Implementations can convert reads of the {\tt time} CSR into loads to
-the memory-mapped {\tt mtime} register, or hard-wire the TM bits in
-{\tt m{\em x}counteren} to 0
+the memory-mapped {\tt mtime} register, or hard-wire the TM bit in
+{\tt mcounteren} to 0
and emulate this functionality in M-mode software.
\end{commentary}