diff options
Diffstat (limited to 'src/machine.tex')
| -rw-r--r-- | src/machine.tex | 26 |
1 files changed, 7 insertions, 19 deletions
diff --git a/src/machine.tex b/src/machine.tex index 57d9cc4..48dce3a 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1802,13 +1802,12 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits %circuitry. %\end{commentary} -\subsection{Counter-Enable Registers ({\tt [m|s]counteren})} +\subsection{Machine Counter-Enable Register ({\tt mcounteren})} \label{sec:mcounteren} -The counter-enable registers {\tt mcounteren} and {\tt scounteren} -are 32-bit registers that -control the availability of the hardware performance-monitoring -counters to the next-lowest privileged mode. +The counter-enable register {\tt mcounteren} is a 32-bit register that +controls the availability of the hardware performance-monitoring counters to +the next-lowest privileged mode. \begin{figure*}[h!] {\footnotesize @@ -1842,12 +1841,12 @@ counters to the next-lowest privileged mode. \end{center} } \vspace{-0.1in} -\caption{Counter-enable registers ({\tt mcounteren} and {\tt scounteren}).} +\caption{Counter-enable register ({\tt mcounteren}).} \label{mcounteren} \end{figure*} -The settings in these registers only control accessibility. The act -of reading or writing these registers does not affect the underlying +The settings in this register only control accessibility. The act +of reading or writing this register does not affect the underlying counters, which continue to increment even when not accessible. When the CY, TM, IR, or HPM{\em n} bit in the {\tt mcounteren} @@ -1858,17 +1857,6 @@ one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode). -If S-mode is implemented, the same bit positions in the {\tt scounteren} -register analogously control access to these registers while executing -in U-mode. If S-mode is permitted to access a counter register and the -corresponding bit is set in {\tt scounteren}, then U-mode is also permitted -to access that register. - -Registers {\tt mcounteren} and {\tt scounteren} are \warl\ registers -that must be implemented if U-mode and S-mode are implemented. -Any of the bits may contain -a hardwired value of zero, indicating reads to the corresponding counter will -cause an illegal instruction exception when executing in a less-privileged mode. \begin{commentary} The counter-enable bits support two common use cases with minimal hardware. For systems that do not need high-performance timers and counters, |