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-rw-r--r--src/machine.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/machine.tex b/src/machine.tex
index af59323..3a8ff5a 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -1479,7 +1479,7 @@ mcycleh}, {\tt minstreth}, and {\tt mhpmcounter{\em n}h} CSRs return bits
On RV128 systems, the 64-bit values in {\tt mcycle}, {\tt minstret}, and
{\tt mhpmcounter{\em n}} are sign-extended to 128-bits when read.
-\begin{commentary}
+\begin{samepage-commentary}
On RV128 systems, both signed and unsigned 64-bit values are held in a
canonical form with bit 63 repeated in all higher bit positions. The
counters are 64-bit values even in RV128, and so the counter CSR reads
@@ -1488,7 +1488,7 @@ implement fewer bits of the counters, provided software would be unlikely
to experience wraparound (e.g., $2^{63}$ instructions executed)
and thereby avoid having to actually implement the sign-extension
circuitry.
-\end{commentary}
+\end{samepage-commentary}
\subsection{Counter-Enable Registers ({\tt [m|h|s]counteren})}
\label{sec:mcounteren}