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@@ -522,16 +522,11 @@ opcode fields.
We use the term {\em exception} to refer to an unusual condition
occurring at run time associated with an instruction in the current
-RISC-V thread. We use the term {\em trap} to refer to the synchronous
+RISC-V hart. We use the term {\em trap} to refer to the synchronous
transfer of control to a trap handler caused by an exceptional
-condition occurring within a RISC-V thread. Trap handlers usually
+condition occurring within a RISC-V hart. Trap handlers usually
execute in a more privileged environment.
-We use the term {\em interrupt} to refer to an external event that
-occurs asynchronously to the current RISC-V thread. When an interrupt
-that must be serviced occurs, some instruction is selected to receive
-an interrupt exception and subsequently experiences a trap.
-
The instruction descriptions in following chapters describe conditions
that raise an exception during execution. Whether and how these are
converted into traps is dependent on the execution environment, though
@@ -540,6 +535,17 @@ trap when an exception is signaled (except for floating-point
exceptions, which, in the standard floating-point extensions, do not
cause traps).
+We use the term {\em interrupt} to refer to an external asynchronous
+event that causes a RISC-V hart to stop execution {\em precisely} on
+some instruction and then to enter an interrupt handler. Some
+execution environments might not make interrupts visible to the
+software running inside an execution environment (e.g., if more
+privileged software implementing the environment respond to external
+interrupts). When interrupts are made visible within an execution
+environment, some software interface must be defined within the
+execution environment to determine and service the cause of the
+interrupt, and to restore regular execution of the interrupted hart.
+
\begin{commentary}
Our use of ``exception'' and ``trap'' matches that in the IEEE-754
floating-point standard.