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diff --git a/src/gmaps.tex b/src/gmaps.tex new file mode 100644 index 0000000..2caaa79 --- /dev/null +++ b/src/gmaps.tex @@ -0,0 +1,75 @@ +\chapter{RV32/64G Instruction Set Listings} + +One goal of the RISC-V project is that it be used as a stable software +development target. For this purpose, we define a combination of a +base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD) as +a ``general-purpose'' ISA, and we use the abbreviation G for the IMAFD +combination of instruction-set extensions. This chapter presents +opcode maps and instruction-set listings for RV32G and RV64G. + +\input{opcode-map} + +Table~\ref{opcodemap} shows a map of the major opcodes for RVG. Major +opcodes with 3 or more lower bits set are reserved for instruction +lengths greater than 32 bits. Opcodes marked as {\em reserved} should +be avoided for custom instruction set extensions as they might be used +by future standard extensions. Major opcodes marked as {\em custom-0} +and {\em custom-1} will be avoided by future standard extensions and +are recommended for use by custom instruction-set extensions within +the base 32-bit instruction format. The opcodes marked {\em + custom-2/rv128} and {\em custom-3/rv128} are reserved for future use +by RV128, but will otherwise be avoided for standard extensions and so +can also be used for custom instruction-set extensions in RV32 and +RV64. + +We believe RV32G and RV64G provide simple but complete instruction +sets for a broad range of general-purpose computing. The optional +compressed instruction set described in Chapter~\ref{compressed} can +be added (forming RV32GC and RV64GC) to improve performance, code +size, and energy efficiency, though with some additional hardware +complexity. + +As we move beyond IMAFDC into further instruction set extensions, the +added instructions tend to be more domain-specific and only provide +benefits to a restricted class of applications, e.g., for multimedia +or security. Unlike most commercial ISAs, the RISC-V ISA design +clearly separates the base ISA and broadly applicable standard +extensions from these more specialized additions. +Chapter~\ref{extensions} has a more extensive discussion of ways to +add extensions to the RISC-V ISA. + +\input{instr-table} + +\FloatBarrier +Table~\ref{rvgcsrnames} lists the CSRs that have +currently been allocated CSR addresses. The timers, counters, and +floating-point CSRs are the only CSRs defined in this specification. + +\begin{table}[htb!] +\begin{center} +\begin{tabular}{|l|l|l|l|} +\hline +Number & Privilege & Name & Description \\ +\hline +\multicolumn{4}{|c|}{Floating-Point Control and Status Registers} \\ +\hline +\tt 0x001 & Read/write &\tt fflags & Floating-Point Accrued Exceptions. \\ +\tt 0x002 & Read/write &\tt frm & Floating-Point Dynamic Rounding Mode. \\ +\tt 0x003 & Read/write &\tt fcsr & Floating-Point Control and Status +Register ({\tt frm} + {\tt fflags}). \\ +\hline +\multicolumn{4}{|c|}{Counters and Timers} \\ +\hline +\tt 0xC00 & Read-only &\tt cycle & Cycle counter for RDCYCLE instruction. \\ +\tt 0xC01 & Read-only &\tt time & Timer for RDTIME instruction. \\ +\tt 0xC02 & Read-only &\tt instret & Instructions-retired counter for RDINSTRET instruction. \\ +\tt 0xC80 & Read-only &\tt cycleh & Upper 32 bits of {\tt cycle}, RV32I only. \\ +\tt 0xC81 & Read-only &\tt timeh & Upper 32 bits of {\tt time}, RV32I only. \\ +\tt 0xC82 & Read-only &\tt instreth & Upper 32 bits of {\tt instret}, RV32I only. \\ +\hline +\end{tabular} +\end{center} +\caption{RISC-V control and status register (CSR) address map.} +\label{rvgcsrnames} +\end{table} + |