diff options
Diffstat (limited to 'src/f.tex')
| -rw-r--r-- | src/f.tex | 20 |
1 files changed, 11 insertions, 9 deletions
@@ -162,8 +162,10 @@ depend on rounding mode when executed with a reserved rounding mode is {\em reserved}, including both static reserved rounding modes (101--110) and dynamic reserved rounding modes (101--111). Some instructions, including widening conversions, have the {\em rm} field but are nevertheless -unaffected by the rounding mode; software should set their {\em rm} -field to RNE (000). +mathematically unaffected by the rounding mode; software should set their +{\em rm} field to RNE (000) but implementations must treat the {\em rm} +field as usual (in particular, with regard to decoding legal vs. reserved +encodings). \begin{table}[htp] \begin{small} @@ -272,7 +274,7 @@ exception flag. \begin{commentary} As allowed by the standard, we do not support traps on floating-point -exceptions in the base ISA, but instead require explicit checks of the flags +exceptions in the F extension, but instead require explicit checks of the flags in software. We considered adding branches controlled directly by the contents of the floating-point accrued exception flags, but ultimately chose to omit these instructions to keep the ISA simple. @@ -322,7 +324,7 @@ Detecting tininess after rounding results in fewer spurious underflow signals. \section{Single-Precision Load and Store Instructions} Floating-point loads and stores use the same base+offset addressing -mode as the integer base ISA, with a base address in register {\em +mode as the integer base ISAs, with a base address in register {\em rs1} and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register {\em rd}. FSW stores a single-precision value from @@ -594,9 +596,9 @@ instructions round according to the {\em rm} field. A floating-point register can be initialized to floating-point positive zero using FCVT.S.W {\em rd}, {\tt x0}, which will never set any exception flags. -All floating-point conversion instructions raise the Inexact exception if the -result differs from its operand value, yet is representable in the destination -format. +All floating-point conversion instructions set the Inexact exception flag if +the rounded result differs from the operand value and the Invalid exception +flag is not set. \vspace{-0.2in} \begin{center} @@ -732,7 +734,7 @@ FMV.W.X & S & 0 & src & 000 & dest & OP-FP \\ The base floating-point ISA was defined so as to allow implementations to employ an internal recoding of the floating-point format in registers to simplify handling of subnormal values and possibly to -reduce functional unit latency. To this end, the base ISA avoids +reduce functional unit latency. To this end, the F extension avoids representing integer values in the floating-point registers by defining conversion and comparison operations that read and write the integer register file directly. This also removes many of the common @@ -782,7 +784,7 @@ FCMP & S & src2 & src1 & EQ/LT/LE & dest & OP-FP \\ \end{center} \begin{commentary} -The F extension provides a $\leq$ comparison, whereas the base ISA provides +The F extension provides a $\leq$ comparison, whereas the base ISAs provide a $\geq$ branch comparison. Because $\leq$ can be synthesized from $\geq$ and vice-versa, there is no performance implication to this inconsistency, but it is nevertheless an unfortunate incongruity in the ISA. |