diff options
Diffstat (limited to 'src/d.tex')
| -rw-r--r-- | src/d.tex | 8 |
1 files changed, 3 insertions, 5 deletions
@@ -18,8 +18,6 @@ as described below in Section~\ref{nanboxing}. FLEN can be 32, 64, or 128 depending on which of the F, D, and Q extensions are supported. There can be up to four different floating-point precisions supported, including H, F, D, and Q. -Half-precision H scalar values are only supported if the V vector -extension is supported. \end{commentary} \section{NaN Boxing of Narrower Values} @@ -222,7 +220,7 @@ number in floating-point register {\em rd}. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. -FCVT.L[U].D and FCVT.D.L[U] are illegal in RV32. +FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.{\em int}.D and the behavior for invalid inputs are the same as for FCVT.{\em int}.S. @@ -319,8 +317,8 @@ FSGNJ & D & src2 & src1 & J[N]/JX & dest & OP-FP \\ \end{tabular} \end{center} -For RV64 only, instructions are provided to move bit patterns between -the floating-point and integer registers. FMV.X.D moves the +For XLEN$>=$64 only, instructions are provided to move bit patterns +between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register {\em rs1} to a representation in IEEE 754-2008 standard encoding in integer register {\em rd}. FMV.D.X moves the double-precision value encoded in IEEE |