diff options
| -rw-r--r-- | src/machine.tex | 8 | ||||
| -rw-r--r-- | src/riscv-privileged.tex | 2 |
2 files changed, 9 insertions, 1 deletions
diff --git a/src/machine.tex b/src/machine.tex index 3472d44..043d584 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -1555,6 +1555,14 @@ Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction. \begin{commentary} + For example, if we name the software-writable SEIP bit {\tt B} and the + signal from the external interrupt controller {\tt E}, then if \mbox{\tt csrrs + t0, mip, t1} is executed, {\tt t0[9]} is written with \mbox{\tt B || E}, then + {\tt B} is written with \mbox{\tt B || t1[9]}. + If \mbox{\tt csrrw t0, mip, t1} is executed, then {\tt t0[9]} is written with + \mbox{\tt B || E}, and {\tt B} is simply written with {\tt t1[9]}. + In neither case does {\tt B} depend upon {\tt E}. + The SEIP field behavior is designed to allow a higher privilege layer to mimic external interrupts cleanly, without losing any real external interrupts. The behavior of the CSR instructions is diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex index bf71aed..cacaf13 100644 --- a/src/riscv-privileged.tex +++ b/src/riscv-privileged.tex @@ -10,7 +10,7 @@ \input{preamble} -\newcommand{\privrev}{20210915-Public-Review-{\em draft}} +\newcommand{\privrev}{20210921-{\em draft}} \newcommand{\privmonthyear}{September 2021} \setcounter{secnumdepth}{3} |