diff options
| -rw-r--r-- | src/hypervisor.adoc | 10 | ||||
| -rw-r--r-- | src/images/bytefield/vsiereg-standard.edn | 18 | ||||
| -rw-r--r-- | src/images/bytefield/vsipreg-standard.edn | 18 | ||||
| -rw-r--r-- | src/priv-csrs.adoc | 91 | ||||
| -rw-r--r-- | src/priv-preface.adoc | 1 | ||||
| -rw-r--r-- | src/resources/themes/riscv-spec.yml | 5 | ||||
| -rw-r--r-- | src/smstateen.adoc | 278 | ||||
| -rw-r--r-- | src/sscofpmf.adoc | 2 | ||||
| -rw-r--r-- | src/sstc.adoc | 3 | ||||
| -rw-r--r-- | src/supervisor.adoc | 2 |
10 files changed, 246 insertions, 182 deletions
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc index 5a66919..d0edb9b 100644 --- a/src/hypervisor.adoc +++ b/src/hypervisor.adoc @@ -1,5 +1,5 @@ [[hypervisor]] -== Hypervisor Extension, Version 1.0 +== "H" Extension for Hypervisor Support, Version 1.0 This chapter describes the RISC-V hypervisor extension, which virtualizes the supervisor-level architecture to support the efficient @@ -976,6 +976,14 @@ include::images/bytefield/vsipreg-standard.edn[] .Standard portion (bits 15:0) of `vsie`. include::images/bytefield/vsiereg-standard.edn[] +When bit 13 of `hideleg` is zero, `vsip`.LCOFIP and `vsie`.LCOFIE +are read-only zeros. +Else, `vsip`.LCOFIP and `vsie`.LCOFIE are aliases of `sip`.LCOFIP +and `sie`.LCOFIE. + +NOTE: The `vsip`.LCOFIP and `vsie`.LCOFIE bits were added in Version 1.13 of +the Privileged Architecture. + When bit 10 of `hideleg` is zero, `vsip`.SEIP and `vsie`.SEIE are read-only zeros. Else, `vsip`.SEIP and `vsie`.SEIE are aliases of `hip`.VSEIP and `hie`.VSEIE. diff --git a/src/images/bytefield/vsiereg-standard.edn b/src/images/bytefield/vsiereg-standard.edn index 52d98a6..c8829cf 100644 --- a/src/images/bytefield/vsiereg-standard.edn +++ b/src/images/bytefield/vsiereg-standard.edn @@ -8,9 +8,11 @@ (def boxes-per-row 32) (draw-box nil {:span 6 :borders {}}) -(draw-box "15" {:borders {}}) -(draw-box nil {:span 4 :borders {}}) -(draw-box "10" {:borders {}}) +(draw-box "15" {:text-anchor "start" :borders {}}) +(draw-box "14" {:text-anchor "end" :borders {}}) +(draw-box "13" {:span 2 :borders {}}) +(draw-box "12" {:text-anchor "start" :borders {}}) +(draw-box "10" {:text-anchor "end" :borders {}}) (draw-box "9" {:span 2 :borders {}}) (draw-box "8" {:borders {}}) (draw-box nil {:borders {}}) @@ -24,7 +26,9 @@ (draw-box nil {:span 7 :borders {}}) (draw-box nil {:span 6 :borders {}}) -(draw-box "0" {:span 6}) +(draw-box "0" {:span 2}) +(draw-box (text "LCOFIE" {:font-size 20}) {:span 2}) +(draw-box "0" {:span 2}) (draw-box "SEIE" {:span 2}) (draw-box "0" {:span 3}) (draw-box "STIE" {:span 2}) @@ -34,7 +38,9 @@ (draw-box nil {:span 7 :borders {}}) (draw-box nil {:span 6 :borders {}}) -(draw-box "6" {:span 6 :borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "3" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) @@ -42,4 +48,4 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:borders {}}) (draw-box nil {:span 7 :borders {}}) -----
\ No newline at end of file +---- diff --git a/src/images/bytefield/vsipreg-standard.edn b/src/images/bytefield/vsipreg-standard.edn index e9baae2..fff25a2 100644 --- a/src/images/bytefield/vsipreg-standard.edn +++ b/src/images/bytefield/vsipreg-standard.edn @@ -8,9 +8,11 @@ (def boxes-per-row 32) (draw-box nil {:span 6 :borders {}}) -(draw-box "15" {:borders {}}) -(draw-box nil {:span 4 :borders {}}) -(draw-box "10" {:borders {}}) +(draw-box "15" {:text-anchor "start" :borders {}}) +(draw-box "14" {:text-anchor "end" :borders {}}) +(draw-box "13" {:span 2 :borders {}}) +(draw-box "12" {:text-anchor "start" :borders {}}) +(draw-box "10" {:text-anchor "end" :borders {}}) (draw-box "9" {:span 2 :borders {}}) (draw-box "8" {:borders {}}) (draw-box nil {:borders {}}) @@ -24,7 +26,9 @@ (draw-box nil {:span 7 :borders {}}) (draw-box nil {:span 6 :borders {}}) -(draw-box "0" {:span 6}) +(draw-box "0" {:span 2}) +(draw-box (text "LCOFIP" {:font-size 20}) {:span 2}) +(draw-box "0" {:span 2}) (draw-box "SEIP" {:span 2}) (draw-box "0" {:span 3}) (draw-box "STIP" {:span 2}) @@ -34,7 +38,9 @@ (draw-box nil {:span 7 :borders {}}) (draw-box nil {:span 6 :borders {}}) -(draw-box "6" {:span 6 :borders {}}) +(draw-box "2" {:span 2 :borders {}}) +(draw-box "1" {:span 2 :borders {}}) +(draw-box "3" {:span 2 :borders {}}) (draw-box "1" {:span 2 :borders {}}) (draw-box "3" {:span 3 :borders {}}) (draw-box "1" {:span 2 :borders {}}) @@ -42,4 +48,4 @@ (draw-box "1" {:span 2 :borders {}}) (draw-box "1" {:borders {}}) (draw-box nil {:span 7 :borders {}}) -----
\ No newline at end of file +---- diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index ac9432e..e799b51 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -282,8 +282,26 @@ Supervisor count overflow. |`0x5A8` |SRW |`scontext` |Supervisor-mode context register. -4+^|Supervisor Resource Management Configuration -|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration. +//4+^|Supervisor Resource Management Configuration +//|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration. + +4+^|Supervisor State Enable Registers +|`0x10C` + + `0x10D` + + `0x10E` + + `0x10F` +|SRW + + SRW + + SRW + + SRW +|`sstateen0` + + `sstateen1` + + `sstateen2` + + `sstateen3` +|Supervisor State Enable 0 Register. + + Supervisor State Enable 1 Register. + + Supervisor State Enable 2 Register. + + Supervisor State Enable 3 Register. |=== @@ -378,6 +396,40 @@ HRW |Delta for VS/VU-mode timer. + Upper 32 bits of `htimedelta`, RV32 only. +4+^|Hypervisor State Enable Registers +|`0x60C` + + `0x60D` + + `0x60E` + + `0x60F` + + `0x61C` + + `0x61D` + + `0x61E` + + `0x61F` +|HRW + + HRW + + HRW + + HRW + + HRW + + HRW + + HRW + + HRW +|`hstateen0` + + `hstateen1` + + `hstateen2` + + `hstateen3` + + `hstateen0h` + + `hstateen1h` + + `hstateen2h` + + `hstateen3h` +|Hypervisor State Enable 0 Register. + + Hypervisor State Enable 1 Register. + + Hypervisor State Enable 2 Register. + + Hypervisor State Enable 3 Register. + + Upper 32 bits of Hypervisor State Enable 0 Register, RV32 only. + + Upper 32 bits of Hypervisor State Enable 1 Register, RV32 only. + + Upper 32 bits of Hypervisor State Enable 2 Register, RV32 only. + + Upper 32 bits of Hypervisor State Enable 3 Register, RV32 only. + 4+^|Virtual Supervisor Registers |`0x200` + @@ -416,6 +468,7 @@ Virtual supervisor trap cause. + Virtual supervisor bad address or instruction. + Virtual supervisor interrupt pending. + Virtual supervisor address translation and protection. + |=== <<< @@ -584,6 +637,40 @@ Physical memory protection address register. + Physical memory protection address register. +   + Physical memory protection address register. + +4+^|Machine State Enable Registers +|`0x30C` + + `0x30D` + + `0x30E` + + `0x30F` + + `0x31C` + + `0x31D` + + `0x31E` + + `0x31F` +|MRW + + MRW + + MRW + + MRW + + MRW + + MRW + + MRW + + MRW +|`mstateen0` + + `mstateen1` + + `mstateen2` + + `mstateen3` + + `mstateen0h` + + `mstateen1h` + + `mstateen2h` + + `mstateen3h` +|Machine State Enable 0 Register. + + Machine State Enable 1 Register. + + Machine State Enable 2 Register. + + Machine State Enable 3 Register. + + Upper 32 bits of Machine State Enable 0 Register, RV32 only. + + Upper 32 bits of Machine State Enable 1 Register, RV32 only. + + Upper 32 bits of Machine State Enable 2 Register, RV32 only. + + Upper 32 bits of Machine State Enable 3 Register, RV32 only. |=== <<< diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc index e8dac15..8e97ecd 100644 --- a/src/priv-preface.adoc +++ b/src/priv-preface.adoc @@ -139,6 +139,7 @@ in `menvcfg` and `henvcfg`. be set to a nonzero value but sometimes not. * Clarified exception behavior of unimplemented or inaccessible CSRs. * Clarified that Svpbmt allows implementations to override additional PMAs. +* Exposed count-overflow interrups to VS-mode. [.big]*_Preface to Version 20211203_* diff --git a/src/resources/themes/riscv-spec.yml b/src/resources/themes/riscv-spec.yml index b09c4e4..ceb6e53 100644 --- a/src/resources/themes/riscv-spec.yml +++ b/src/resources/themes/riscv-spec.yml @@ -80,8 +80,9 @@ codespan: menu_caret_content: " <font size=\"1.15em\"><color rgb=\"000000\">\u203a</color></font> " heading: align: left - margin_bottom: 0.25in - margin_top: 0.5in + margin_bottom: $block_margin_bottom + #margin_top: 0.25in + margin_top: $block_margin_bottom min_height_after: auto font_color: 000000 font_family: headings diff --git a/src/smstateen.adoc b/src/smstateen.adoc index beebc4f..f0fdea0 100644 --- a/src/smstateen.adoc +++ b/src/smstateen.adoc @@ -1,17 +1,15 @@ [[smstateen]] == "Smstateen/Ssstateen" Extensions, Version 1.0.0 -=== Motivation - The implementation of optional RISC-V extensions has the potential to open covert channels between separate user threads, or between separate guest OSes running under a hypervisor. The problem occurs when an extension adds processor -state---usually explicit registers, but possibly other forms of state---that +state -- usually explicit registers, but possibly other forms of state -- that the main OS or hypervisor is unaware of (and hence won't context-switch) but that can be modified/written by one user thread or guest OS and perceived/examined/read by another. -For example, the proposed Advanced Interrupt Architecture (AIA) for RISC-V adds +For example, the Advanced Interrupt Architecture (AIA) for RISC-V adds to a hart as many as ten supervisor-level CSRs (`siselect`, `sireg`, `stopi`, `sseteipnum`, `sclreipnum`, `sseteienum`, `sclreienum`, `sclaimei`, `sieh`, and `siph`) and provides also the option for hardware to be backward-compatible with older, @@ -41,63 +39,31 @@ extensions. In any event, there is no need to strain `sstatus` (and add `sstatus for this purpose. The "enable" flags that are needed to plug covert channels are not generally expected to require swapping on context switches of user threads, making them a less-than-compelling candidate for inclusion in `sstatus`. -Hence, a new place is proposed for them instead. - -=== Proposal - -These extensions collectively specify machine-mode and supervisor-mode features. The Smstateen extension specification comprises the mstateen*, sstateen*, and hstateen* CSRs and their functionality. The Ssstateen extension specification comprises only the sstateen* and hstateen* CSRs and their functionality. +Hence, a new place is provided for them instead. -For RV64 harts, this extension adds four new 64-bit CSRs at machine level, -listed with their CSR addresses: +=== State Enable Extensions -`0x30C mstateen0` (Machine State Enable 0) +The Smstateen and Ssstateen extensions collectively specify machine-mode and +supervisor-mode features. The Smstateen extension specification comprises the +mstateen*, sstateen*, and hstateen* CSRs and their functionality. The Ssstateen +extension specification comprises only the sstateen* and hstateen* CSRs and their +functionality. -`0x30D mstateen1` - -`0x30E mstateen2` - -`0x30F mstateen3` +For RV64 harts, this extension adds four new 64-bit CSRs at machine level: +`mstateen0` (Machine State Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at supervisor level: - -`0x10C sstateen0` - -`0x10D sstateen1` - -`0x10E sstateen2` - -`0x10F sstateen3` +`sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, another set of CSRs is added: - -`0x60C hstateen0` - -`0x60D hstateen1` - -`0x60E hstateen2` - -`0x60F hstateen3` +`hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - -`0x31C mstateen0h` - -`0x31D mstateen1h` - -`0x31E mstateen2h` - -`0x31F mstateen3h` - -`0x61C hstateen0h` - -`0x61D hstateen1h` - -`0x61E hstateen2h` - -`0x61F hstateen3h` +`mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, +`hstateen0h`, `hstateen1h`, `hstateen2h`, and `hstateen3h`. For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will @@ -185,18 +151,20 @@ the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way. For each `mstateen` CSR, bit 63 is defined to control access to the -matching `sstateen` and `hstateen` CSRs. -That is, bit 63 of `mstateen0` controls access to `sstateen0` and `hstateen0`; -bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; etc. -Likewise, bit 63 of each `hstateen` correspondingly controls access to -the matching `sstateen` CSR. -A hypervisor may need this control over -accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine an -extension that is supposed to be affected by a bit in an `sstateen` CSR. (Even if -such emulation is uncommon, it should not be excluded.) Machine-level software -needs identical control to be able to emulate the hypervisor extension. (That -is, machine level needs control over accesses to the supervisor-level `sstateen` -CSRs in order to emulate the `hstateen` CSRs, which have such control.) +matching `sstateen` and `hstateen` CSRs. That is, bit 63 of `mstateen0` controls +access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to +`sstateen1` and `hstateen1`; etc. Likewise, bit 63 of each `hstateen` +correspondingly controls access to the matching `sstateen` CSR. + +A hypervisor may need this control over accesses to the `sstateen` CSRs if it +ever must emulate for a virtual machine an extension that is supposed to be +affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, +it should not be excluded. + +Machine-level software needs identical control to be able to emulate the +hypervisor extension. That is, machine level needs control over accesses to the +supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which +have such control. Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is @@ -205,50 +173,16 @@ attempts to access the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always writable (not read-only). -[wavedrom, ,svg] -.... -{reg: [ -{bits: 1, name: 'C'}, -{bits: 1, name: 'FCSR'}, -{bits: 1, name: 'JVT'}, -{bits: 61, name: 'WPRI'} -], config:{bits: 64, lanes: 4, hspace:1024}} -.... - -The C bit controls access to any and all custom state. - -[NOTE] -==== -Bit 0 of these registers is not custom state itself; it is a standard field of -a standard CSR, either mstateen0, hstateen0, or sstateen0. The -requirements that non-standard extensions must meet to be conforming are not -relaxed due solely to changes in the value of this bit. In particular, if -software sets this bit but does not execute any custom instructions or access -any custom state, the software must continue to execute as specified by all -relevant RISC-V standards, or the hardware is not standard-conforming. -The FCSR bit controls access to fcsr for the case when floating-point -instructions operate on x registers instead of f registers as specified by -the Zfinx and related extensions (Zdinx, etc.). Whenever misa.F = 1, bit 1 of -mstateen0 is read-only zero (and hence read-only zero in hstateen0 and -sstateen0 too). For convenience, when the stateen CSRs are implemented and -misa.F = 0, then if bit 1 of a controlling stateen0 CSR is zero, all -floating-point instructions cause an illegal instruction trap (or virtual -instruction trap, if relevant), as though they all access fcsr, regardless of -whether they really do. -==== - -The JVT bit controls access to the JVT CSR provided by the Zcmt extension. - -=== Machine State Enable Register (mstateen0) +=== State Enable 0 Registers +.Machine State Enable 0 Register (`mstateen0`) [wavedrom, ,svg] .... {reg: [ {bits: 1, name: 'C'}, {bits: 1, name: 'FCSR'}, {bits: 1, name: 'JVT'}, -{bits: 52, name: 'WPRI'}, -{bits: 1, name: 'P1P14'}, +{bits: 53, name: 'WPRI'}, {bits: 1, name: 'P1P13'}, {bits: 1, name: 'CONTEXT'}, {bits: 1, name: 'IMSIC'}, @@ -260,37 +194,7 @@ The JVT bit controls access to the JVT CSR provided by the Zcmt extension. ], config: {bits: 64, lanes: 4, hspace:1024}} .... -The C bit controls access to any and all custom state. The FCSR and the JVT -bits control access to the same state as controlled by the same bits in the -sstateen0 CSR. - -The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, -and the sstateen0 CSRs. - -The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, -and the senvcfg CSRs. - -The CSRIND bit in mstateen0 controls access to the siselect, sireg*, -vsiselect, and the vsireg* CSRs provided by the Sscsrind extensions. - -The IMSIC bit in mstateen0 controls access to the IMSIC state, including -CSRs stopei and vstopei, provided by the Ssaia extension. - -The AIA bit in mstateen0 controls access to all state introduced by the -Ssaia extension and is not controlled by either the CSRIND or the IMSIC -bits. - -The CONTEXT bit in mstateen0 controls access to the scontext and -hcontext CSRs provided by the Sdtrig ISA extension. - -The P1P13 bit in mstateen0 controls access to the hedelegh introduced by -Privileged Specification Version 1.13. - -The P1P14 bit in mstateen0 controls access to the srmcfg CSR introduced by -Privileged Specification Version 1.14. - -=== Hypervisor State Enable Register (hstateen0) - +.Hypervisor State Enable 0 Register (`hstateen0`) [wavedrom, ,svg] .... {reg: [ @@ -308,31 +212,84 @@ Privileged Specification Version 1.14. ], config: {bits: 64, lanes: 4, hspace:1024}} .... -The C bit controls access to any and all custom state. The FCSR and the JVT -bits control access to the same state as controlled by the same bits in the -sstateen0 CSR. +.Supervisor State Enable 0 Register (`sstateen0`) +[wavedrom, ,svg] +.... +{reg: [ +{bits: 1, name: 'C'}, +{bits: 1, name: 'FCSR'}, +{bits: 1, name: 'JVT'}, +{bits: 29, name: 'WPRI'} +], config:{bits: 32, lanes: 2, hspace:1024}} +.... -The SE0 bit in hstateen0 controls access to the sstateen0 CSR. +The C bit controls access to any and all custom state. This bit is not custom +state itself. The C bit of these registers is not custom state itself; it is a +standard field of a standard CSR, either `mstateen0`, `hstateen0`, or +`sstateen0`. -The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs. -The CSRIND bit in hstateen0 controls access to the siselect and the -sireg*, (really vsiselect and vsireg*) CSRs provided by the -Sscsrind extensions. +[NOTE] +==== +The requirements that non-standard extensions must meet to be conforming are not +relaxed due solely to changes in the value of this bit. In particular, if +software sets this bit but does not execute any custom instructions or access +any custom state, the software must continue to execute as specified by all +relevant RISC-V standards, or the hardware is not standard-conforming. +==== + +The FCSR bit controls access to `fcsr` for the case when floating-point +instructions operate on `x` registers instead of `f` registers as specified by +the Zfinx and related extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit +of `mstateen0` is read-only zero (and hence read-only zero in `hstateen0` and +`sstateen0` too). For convenience, when the `stateen` CSRs are implemented and +`misa.F` = 0, then if the FCSR bit of a controlling `stateen0` CSR is zero, all +floating-point instructions cause an illegal instruction trap (or virtual +instruction trap, if relevant), as though they all access `fcsr`, regardless of +whether they really do. -The IMSIC bit in hstateen0 controls access to the guest IMSIC state, -including CSRs stopei (really vstopei), provided by the Ssaia extension. +The JVT bit controls access to the `JVT` CSR provided by the Zcmt extension. + +The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, +and the `sstateen0` CSRs. The SE0 bit in `hstateen0` controls access to the +`sstateen0` CSR. + +The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, +and the `senvcfg` CSRs. The ENVCFG bit in `hstateen0` controls access to the +`senvcfg` CSRs. + +The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, +`vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. +The CSRIND bit in `hstateen0` controls access to the `siselect` and the +`sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind +extensions. + +The IMSIC bit in `mstateen0` controls access to the IMSIC state, including +CSRs `stopei` and `vstopei`, provided by the Ssaia extension. The IMSIC bit in +`hstateen0` controls access to the guest IMSIC state, including CSRs `stopei` +(really `vstopei`), provided by the Ssaia extension. [NOTE] ==== -Setting the IMSIC bit in hstateen0 to zero prevents a virtual machine from -accessing the hart's IMSIC the same as setting hstatus.VGEIN = 0. -The AIA bit in hstateen0 controls access to all state introduced by the -Ssaia extension and is not controlled by either the CSRIND or the IMSIC -bits of hstateen0. +Setting the IMSIC bit in `hstateen0` to zero prevents a virtual machine from +accessing the hart's IMSIC the same as setting `hstatus.`VGEIN = 0. ==== -The CONTEXT bit in hstateen0 controls access to the scontext CSR -provided by the Sdtrig ISA extension. +The AIA bit in `mstateen0` controls access to all state introduced by the +Ssaia extension and is not controlled by either the CSRIND or the IMSIC +bits. The AIA bit in `hstateen0` controls access to all state introduced by the +Ssaia extension and is not controlled by either the CSRIND or the IMSIC +bits of `hstateen0`. + +The CONTEXT bit in `mstateen0` controls access to the `scontext` and +`hcontext` CSRs provided by the Sdtrig extension. The CONTEXT bit in +`hstateen0` controls access to the `scontext` CSR provided by the Sdtrig +extension. + +The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by +Privileged Specification Version 1.13. + +//The P1P14 bit in mstateen0 controls access to the srmcfg CSR introduced by +//Privileged Specification Version 1.14. === Usage @@ -375,34 +332,34 @@ at that level. This situation is expected to be common for machine level, and it might also arise, for example, for a type-1 hypervisor that hosts only a single guest virtual machine. -=== Possible expansion - +[NOTE] +==== If a need is anticipated, the set of `stateen` CSRs could in the future be doubled by adding these: -`0x38C mstateen4` `0x39C mstateen4h` +* `0x38C mstateen4`, `0x39C mstateen4h` -`0x38D mstateen5` `0x39D mstateen5h` +* `0x38D mstateen5`, `0x39D mstateen5h` -`0x38E mstateen6` `0x39E mstateen6h` +* `0x38E mstateen6`, `0x39E mstateen6h` -`0x38F mstateen7` `0x39F mstateen7h` +* `0x38F mstateen7`, `0x39F mstateen7h` -`0x18C sstateen4` +* `0x18C sstateen4` -`0x18D sstateen5` +* `0x18D sstateen5` -`0x18E sstateen6` +* `0x18E sstateen6` -`0x18F sstateen7` +* `0x18F sstateen7` -`0x68C hstateen4` `0x69C hstateen4h` +* `0x68C hstateen4`, `0x69C hstateen4h` -`0x68D hstateen5` `0x69D hstateen5h` +* `0x68D hstateen5`, `0x69D hstateen5h` -`0x68E hstateen6` `0x69E hstateen6h` +* `0x68E hstateen6`, `0x69E hstateen6h` -`0x68F hstateen7` `0x69F hstateen7h` +* `0x68F hstateen7`, `0x69F hstateen7h` These additional CSRs are not a definite part of the original proposal because it is unclear whether they will ever be needed, and it is believed the rate of @@ -410,3 +367,4 @@ consumption of bits in the first group, registers numbered 0-3, will be slow enough that any looming shortage will be perceptible many years in advance. At the moment, it is not known even how many years it may take to exhaust just `mstateen0`, `sstateen0`, and `hstateen0`. +==== diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc index b19f491..7eb8cf2 100644 --- a/src/sscofpmf.adoc +++ b/src/sscofpmf.adoc @@ -84,7 +84,6 @@ LCOFIP bit is cleared by software before servicing the count overflow interrupt resulting from one or more count overflows. [NOTE] -.Non-normative ==== There are not separate overflow status and overflow interrupt enable bits. In practice, enabling overflow interrupt generation (by clearing the OF bit) is @@ -94,7 +93,6 @@ overflow interrupt can be generated. ==== [NOTE] -.Non-normative ==== Software can distinguish newly overflowed counters (yet to be serviced by an overflow interrupt handler) from overflowed counters that have already been diff --git a/src/sstc.adoc b/src/sstc.adoc index 078cc50..a96ea87 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -47,7 +47,6 @@ time - typically as a result of writing stimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules. [NOTE] -.Non-normative ==== A spurious timer interrupt might occur if an interrupt handler advances stimecmp then immediately returns, because STIP might not yet have fallen in @@ -58,7 +57,6 @@ poll STIP until it falls. ==== [NOTE] -.Non-normative ==== In systems in which a supervisor execution environment (SEE) provides timer facilities via an SBI function call, this SBI call will continue to support @@ -134,7 +132,6 @@ typically as a result of writing vstimecmp. The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1. [NOTE] -.Non-normative ==== In systems in which a supervisor execution environment (SEE) implemented by an HS-mode hypervisor provides timer facilities via an SBI function call, this SBI diff --git a/src/supervisor.adoc b/src/supervisor.adoc index eb1a45a..636c3bf 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -2094,6 +2094,7 @@ gratuitous page-fault, the performance benefit of omitting the memory-management fence instructions outweighs the occasional cost of a gratuitous page-fault. ==== +//// [[sec:ssqosid]] == "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0 @@ -2214,3 +2215,4 @@ the new context, it switches to the new VM's `srmcfg`. The supervisor can also use a separate configuration for execution not to be attributed to either contexts. ==== +//// |