diff options
| -rw-r--r-- | src/hypervisor.tex | 5 | ||||
| -rw-r--r-- | src/machine.tex | 39 | ||||
| -rw-r--r-- | src/priv-intro.tex | 12 |
3 files changed, 14 insertions, 42 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 98a54ac..2bb1372 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -496,7 +496,10 @@ virtualization modes (V=0 to V=1, or vice-versa), the implementation swaps the defined fields of {\tt bsip} with their counterparts in {\tt sip}. The other fields in {\tt sip} are unchanged. -\note{AW: Need to describe how {\tt bsip}.SEIP interacts with PLIC. I think {\tt bsip}.SEIP should purely be a read-write storage bit to emulate the PLIC for VS-mode; the PLIC should not be wired into {\tt bsip}.SEIP.} +\note{Need to describe how {\tt bsip}.SEIP interacts with PLIC. Current +thinking is that {\tt bsip}.SEIP should purely be a read-write storage bit to +emulate the PLIC for VS-mode; the PLIC should not be wired into {\tt +bsip}.SEIP.} \begin{figure*}[h!] {\footnotesize diff --git a/src/machine.tex b/src/machine.tex index a22d076..ccf2ace 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -3,8 +3,7 @@ This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V -system. M-mode is the only mandatory privilege mode in a RISC-V -hardware implementation. M-mode is used for low-level access to a +system. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA @@ -88,17 +87,6 @@ at a time. If zero after one shift, then the machine is RV32. If zero after two shifts, then the machine is RV64, else RV128. \end{commentary} -When MXL is set to a value less than the widest supported XLEN, all -operations must ignore source operand register bits above the -configured XLEN, and must sign-extend results to fill the entire -widest supported XLEN in the destination register. - -\begin{commentary} -We require that operations always fill the entire underlying hardware -registers with defined values to avoid implementation-defined -behavior. -\end{commentary} - The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension ``A'' , bit 1 encodes presence of extension ``B'', @@ -129,7 +117,7 @@ The ``X'' bit will be set if there are any non-standard extensions. Bit & Character & Description \\ \hline 0 & A & Atomic extension \\ - 1 & B & {\em Tentatively reserved for Bit operations extension} \\ + 1 & B & {\em Tentatively reserved for Bit-Manipulation extension} \\ 2 & C & Compressed extension \\ 3 & D & Double-precision floating-point extension \\ 4 & E & RV32E base ISA \\ @@ -196,8 +184,6 @@ If an instruction that would write {\tt misa} increases IALIGN, and the subsequent instruction's address is not IALIGN-bit aligned, the write to {\tt misa} is suppressed, leaving {\tt misa} unchanged. -\clearpage - \subsection{Machine Vendor ID Register {\tt mvendorid}} The {\tt mvendorid} CSR is a 32-bit read-only register providing @@ -603,13 +589,6 @@ supported in systems running Unix-like operating systems to support user-level trap handling. \end{commentary} -\begin{commentary} -Fields that were previously allocated for H-mode support in {\tt - mstatus} have now been reserved as \wpri\ fields. To reduce -backwards incompatibility with existing implementations, we did not -compact the register after removing these fields. -\end{commentary} - \subsection{Base ISA Control in {\tt mstatus} Register} \label{xlen-control} @@ -637,8 +616,11 @@ Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register. - \begin{commentary} +We require that operations always fill the entire underlying hardware +registers with defined values to avoid implementation-defined +behavior. + To reduce hardware complexity, the architecture imposes no checks that lower-privilege modes have XLEN settings less than or equal to the next-higher privilege mode. In practice, such settings would almost @@ -741,7 +723,7 @@ operation is permitted in S-mode. TSR is hard-wired to 0 when S-mode is not supported. \begin{commentary} -Trapping SRET is necessary to emulate the Augmented Virtualization mechanism +Trapping SRET is necessary to emulate the hypervisor extension (see Chapter~\ref{hypervisor}) on implementations that do not provide it. \end{commentary} @@ -1717,10 +1699,9 @@ read-only shadows of {\tt mcycle}, {\tt minstret}, and {\tt mhpmcounter{\em n}}, respectively. The {\tt time} CSR is a read-only shadow of the memory-mapped {\tt mtime} register. \begin{commentary} -Implementations can convert reads of the {\tt time} CSR into loads to -the memory-mapped {\tt mtime} register, or hard-wire the TM bit in -{\tt mcounteren} to 0 -and emulate this functionality in M-mode software. +Implementations can convert reads of the {\tt time} CSR into loads to the +memory-mapped {\tt mtime} register, or emulate this functionality in M-mode +software. \end{commentary} \subsection{Machine Counter-Inhibit CSR ({\tt mcountinhibit})} diff --git a/src/priv-intro.tex b/src/priv-intro.tex index 723b9b4..7787f69 100644 --- a/src/priv-intro.tex +++ b/src/priv-intro.tex @@ -142,18 +142,6 @@ manage secure execution environments on RISC-V. User-mode (U-mode) and supervisor-mode (S-mode) are intended for conventional application and operating system usage respectively. -\begin{commentary} -The previous Hypervisor mode (H-mode) designed to support Type-1 -hypervisors has been removed and the encoding space reserved as we are -focusing on hypervisor support via an extended S mode suitable for -both Type-1 and Type-2 hypervisors as described in -Chapter~\ref{hypervisor}. The encoding space for H is reserved for -future use and to avoid backwards incompatible changes in bit -positions in various status registers. The bit positions might be -reused in the future for different Type-1 hypervisor support or -possibly additional secure execution modes. -\end{commentary} - Each privilege level has a core set of privileged ISA extensions with optional extensions and variants. For example, machine-mode supports an optional standard extension for memory protection. Also, supervisor mode can be |