2 files changed, 57 insertions, 32 deletions

diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index 2b01e74..153fbe2 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -1302,17 +1302,31 @@ instructions that normally read or modify {\tt sstatus} actually access
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\scalebox{0.95}{
-\begin{tabular}{cWcccccWccccWcc}
+\begin{tabular}{cEcccc}
 \\
 \instbit{31} &
 \instbitrange{30}{20} &
 \instbit{19} &
 \instbit{18} &
 \instbit{17} &
+ \\
+\hline
+\multicolumn{1}{|c|}{SD} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{MXR} &
+\multicolumn{1}{c|}{SUM} &
+\multicolumn{1}{c|}{\wpri} &
+ \\
+\hline
+1 & 11 & 1 & 1 & 1 & \\
+\end{tabular}
+\begin{tabular}{cWWWWccccWcc}
+\\
+&
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
-\instbitrange{12}{9} &
+\instbitrange{12}{11} &
+\instbitrange{10}{9} &
 \instbit{8} &
 \instbit{7} &
 \instbit{6} &
@@ -1321,24 +1335,21 @@ instructions that normally read or modify {\tt sstatus} actually access
 \instbit{1} &
 \instbit{0} \\
 \hline
-\multicolumn{1}{|c|}{SD} &
-\multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{MXR} &
-\multicolumn{1}{c|}{SUM} &
-\multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{XS[1:0]} &
+ &
+\multicolumn{1}{|c|}{XS[1:0]} &
 \multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{SIE}  &
+\multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{\wpri} \\
 \hline
-1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
-\end{tabular}}
+ & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
+\end{tabular}
 \end{center}
 }
 \vspace{-0.1in}
@@ -1372,12 +1383,13 @@ instructions that normally read or modify {\tt sstatus} actually access
 \hline
 1 & VSXLEN-35 & 2 & 12 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cWWFccccWcc}
+\begin{tabular}{cWWWWccccWcc}
 \\
 &
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
-\instbitrange{12}{9} &
+\instbitrange{12}{11} &
+\instbitrange{10}{9} &
 \instbit{8} &
 \instbit{7} &
 \instbit{6} &
@@ -1390,6 +1402,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \multicolumn{1}{|c|}{XS[1:0]} &
 \multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
@@ -1398,7 +1411,7 @@ instructions that normally read or modify {\tt sstatus} actually access
 \multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{\wpri} \\
 \hline
- & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
+ & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }
diff --git a/src/supervisor.tex b/src/supervisor.tex
index 76cadf1..45fa5bd 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -46,17 +46,31 @@ register keeps track of the processor's current operating state.
 {\footnotesize
 \begin{center}
 \setlength{\tabcolsep}{4pt}
-\scalebox{0.95}{
-\begin{tabular}{cWcccccWccccWcc}
+\begin{tabular}{cEcccc}
 \\
 \instbit{31} &
 \instbitrange{30}{20} &
 \instbit{19} &
 \instbit{18} &
 \instbit{17} &
+ \\
+\hline
+\multicolumn{1}{|c|}{SD} &
+\multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{MXR} &
+\multicolumn{1}{c|}{SUM} &
+\multicolumn{1}{c|}{\wpri} &
+ \\
+\hline
+1 & 11 & 1 & 1 & 1 & \\
+\end{tabular}
+\begin{tabular}{cWWWWccccWcc}
+\\
+&
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
-\instbitrange{12}{9} &
+\instbitrange{12}{11} &
+\instbitrange{10}{9} &
 \instbit{8} &
 \instbit{7} &
 \instbit{6} &
@@ -65,25 +79,21 @@ register keeps track of the processor's current operating state.
 \instbit{1} &
 \instbit{0} \\
 \hline
-\multicolumn{1}{|c|}{SD} &
-\multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{MXR} &
-\multicolumn{1}{c|}{SUM} &
-\multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{XS[1:0]} &
+ &
+\multicolumn{1}{|c|}{XS[1:0]} &
 \multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
 \multicolumn{1}{c|}{SPIE} &
 \multicolumn{1}{c|}{\wpri} &
-\multicolumn{1}{c|}{SIE}  &
-\multicolumn{1}{c|}{\wpri}
-\\
+\multicolumn{1}{c|}{SIE} &
+\multicolumn{1}{c|}{\wpri} \\
 \hline
-1 & 11 & 1 & 1 & 1 & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
-\end{tabular}}
+ & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
+\end{tabular}
 \end{center}
 }
 \vspace{-0.1in}
@@ -117,12 +127,13 @@ register keeps track of the processor's current operating state.
 \hline
 1 & 29 & 2 & 12 & 1 & 1 & 1 & \\
 \end{tabular}
-\begin{tabular}{cWWFccccWcc}
+\begin{tabular}{cWWWWccccWcc}
 \\
 &
 \instbitrange{16}{15} &
 \instbitrange{14}{13} &
-\instbitrange{12}{9} &
+\instbitrange{12}{11} &
+\instbitrange{10}{9} &
 \instbit{8} &
 \instbit{7} &
 \instbit{6} &
@@ -135,6 +146,7 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{|c|}{XS[1:0]} &
 \multicolumn{1}{c|}{FS[1:0]} &
 \multicolumn{1}{c|}{\wpri} &
+\multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{SPP} &
 \multicolumn{1}{c|}{\wpri} &
 \multicolumn{1}{c|}{UBE} &
@@ -143,7 +155,7 @@ register keeps track of the processor's current operating state.
 \multicolumn{1}{c|}{SIE} &
 \multicolumn{1}{c|}{\wpri} \\
 \hline
- & 2 & 2 & 4 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
+ & 2 & 2 & 2 & 2 & 1 & 1 & 1 & 1 & 3 & 1 & 1 \\
 \end{tabular}
 \end{center}
 }