3 files changed, 16 insertions, 0 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex
index 872177a..70e082c 100644
--- a/src/hypervisor.tex
+++ b/src/hypervisor.tex
@@ -856,6 +856,11 @@ requirement to order main memory accesses.
 Table~\ref{tab:henvcfg-FIOM} details the modified interpretation of
 FENCE instruction bits PI, PO, SI, and SO when FIOM=1 and V=1.
 
+Similarly, when FIOM=1 and V=1,
+if an atomic instruction that accesses a region ordered as device I/O
+has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered
+as though it accesses both device I/O and memory.
+
 \begin{table}[h!]
 \begin{center}
 \begin{tabular}{|c|l|}
diff --git a/src/machine.tex b/src/machine.tex
index 4ecc7ec..ae4b5f6 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2351,6 +2351,12 @@ to order main memory accesses.
 Table~\ref{tab:menvcfg-FIOM} details the modified interpretation of
 FENCE instruction bits PI, PO, SI, and SO for modes less privileged than M
 when FIOM=1.
+
+Similarly, for modes less privileged than M when FIOM=1,
+if an atomic instruction that accesses a region ordered as device I/O
+has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered
+as though it accesses both device I/O and memory.
+
 If U-mode is not supported, FIOM is hardwired to zero.
 
 \begin{table}[h!]
diff --git a/src/supervisor.tex b/src/supervisor.tex
index ace6fe2..109a69c 100644
--- a/src/supervisor.tex
+++ b/src/supervisor.tex
@@ -840,6 +840,11 @@ to order main memory accesses.
 Table~\ref{tab:senvcfg-FIOM} details the modified interpretation of
 FENCE instruction bits PI, PO, SI, and SO in U-mode when FIOM=1.
 
+Similarly, for U-mode when FIOM=1,
+if an atomic instruction that accesses a region ordered as device I/O
+has its {\em aq} and/or {\em rl} bit set, then that instruction is ordered
+as though it accesses both device I/O and memory.
+
 \begin{table}[h!]
 \begin{center}
 \begin{tabular}{|c|l|}