diff options
| -rw-r--r-- | src/preface.tex | 7 | ||||
| -rw-r--r-- | src/rv64.tex | 19 |
2 files changed, 18 insertions, 8 deletions
diff --git a/src/preface.tex b/src/preface.tex index dd37bd5..ad1681d 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -61,6 +61,13 @@ The major changes in this version of the document include: environment interfaces rather then just mandating invisible handling of misaligned loads and stores in user mode. This behavior was already needed for definition of classic privileged architecture. +\item FENCE.TSO instruction extension added. +\item Removed prohibitions on using RV32E with other extensions. +\item Removed platform-specific mandates that certain encodings + produced illegal instruction exceptions in RV32E and RV64I chapters. +\item Counter/timer instructions are now not considered part of + mandatory base ISA, and so CSR instructions were moved into separate + chapter. \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, and changed their behavior on signaling-NaN inputs to conform to the minimumNumber and maximumNumber operations in the proposed IEEE 754-201x diff --git a/src/rv64.tex b/src/rv64.tex index e4bfb3c..0aaf127 100644 --- a/src/rv64.tex +++ b/src/rv64.tex @@ -17,7 +17,7 @@ Additional instruction variants are provided to manipulate 32-bit values in RV64I, indicated by a `W' suffix to the opcode. These ``*W'' instructions ignore the upper 32 bits of their inputs and always produce 32-bit signed values, i.e. bits XLEN-1 through 31 are -equal. They cause an illegal instruction exception in RV32I. +equal. \begin{commentary} The compiler and calling convention maintain an invariant that all 32-bit @@ -56,7 +56,7 @@ I-immediate[11:0] & src & ADDIW & dest & OP-IMM-32 \\ \end{tabular} \end{center} -ADDIW is an RV64I-only instruction that adds the sign-extended 12-bit +ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register {\em rs1} and produces the proper sign-extension of a 32-bit result in {\em rd}. Overflows are ignored and the result is the low 32 bits of the result sign-extended to 64 bits. Note, @@ -101,14 +101,18 @@ shifted is in {\em rs1}, and the shift amount is encoded in the lower encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the -original sign bit is copied into the vacated upper bits). For RV32I, -SLLI, SRLI, and SRAI generate an illegal instruction exception if -$imm[5] \neq 0$. +original sign bit is copied into the vacated upper bits). SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate on 32-bit values and produce -signed 32-bit results. SLLIW, SRLIW, and SRAIW generate an illegal -instruction exception if $imm[5] \neq 0$. +signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings +with $imm[5] \neq 0$ are reserved. + +\begin{commentary} + Previously, SLLIW, SRLIW, and SRAIW with imm[5]=0 were defined to + cause illegal instruction exceptions, whereas now they are marked as + reserved. This is a backwards-compatible change. +\end{commentary} \vspace{-0.2in} \begin{center} @@ -128,7 +132,6 @@ U-immediate[31:12] & dest & AUIPC \end{tabular} \end{center} - LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 20-bit U-immediate into bits 31--12 of register {\em rd} and places zero in the lowest 12 bits. The 32-bit result is |