diff options
| -rw-r--r-- | src/hypervisor.tex | 2 | ||||
| -rw-r--r-- | src/machine.tex | 56 | ||||
| -rw-r--r-- | src/priv-csrs.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 36 |
4 files changed, 48 insertions, 48 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index e5696d4..30fd913 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -94,7 +94,7 @@ HS-mode's version. When V=1, the background supervisor CSRs contain HS-mode's version, and the foreground supervisor CSRs contain the S-mode guest's version. The background registers are accessible to HS-mode, but not to S-mode. -In this section, we use the term {\em HS-XLEN} to refer to the effective XLEN +In this section, we use the term {\em HSXLEN} to refer to the effective XLEN when executing in HS-mode. \subsection{Hypervisor Virtual Trap Value ({\tt hvtval}) Register} diff --git a/src/machine.tex b/src/machine.tex index e71e2f2..7655fe5 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -50,7 +50,7 @@ mechanism. The MXL (Machine XLEN) field encodes the native base integer ISA width as shown in Table~\ref{misabase}. The MXL field may be writable in implementations that support multiple base ISA widths. The effective -XLEN in M-mode, {\em M-XLEN}, is given by the setting of MXL, or has a +XLEN in M-mode, {\em MXLEN}, is given by the setting of MXL, or has a fixed value if {\tt misa} is zero. The MXL field is always set to the widest supported ISA variant at reset. @@ -70,9 +70,9 @@ MXL & XLEN \\ \label{misabase} \end{table*} -The {\tt misa} CSR is M-XLEN bits wide. If the value read from {\tt misa} is -nonzero, field MXL of that value always denotes the current M-XLEN. If a write -to {\tt misa} causes M-XLEN to change, the position of MXL moves to the +The {\tt misa} CSR is MXLEN bits wide. If the value read from {\tt misa} is +nonzero, field MXL of that value always denotes the current MXLEN. If a write +to {\tt misa} causes MXLEN to change, the position of MXL moves to the most-significant two bits of {\tt misa} at the new width. \begin{commentary} @@ -230,7 +230,7 @@ manufacturer ID with JEDEC has a one-time cost of \$500. \subsection{Machine Architecture ID Register {\tt marchid}} -The {\tt marchid} CSR is an M-XLEN-bit read-only register encoding the +The {\tt marchid} CSR is an MXLEN-bit read-only register encoding the base microarchitecture of the hart. This register must be readable in any implementation, but a value of 0 can be returned to indicate the field is not implemented. The combination of {\tt mvendorid} and {\tt @@ -258,7 +258,7 @@ Open-source project architecture IDs are allocated globally by the RISC-V Foundation, and have non-zero architecture IDs with a zero most-significant-bit (MSB). Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and -cannot contain zero in the remaining M-XLEN-1 bits. +cannot contain zero in the remaining MXLEN-1 bits. \begin{commentary} The intent is for the architecture ID to represent the @@ -318,7 +318,7 @@ boundaries to ease human readability. \subsection{Hart ID Register {\tt mhartid}} -The {\tt mhartid} CSR is an M-XLEN-bit read-only register +The {\tt mhartid} CSR is an MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. This register must be readable in any implementation. Hart IDs might not necessarily be numbered contiguously in a multiprocessor system, @@ -353,7 +353,7 @@ of the largest hart ID used in a system. \subsection{Machine Status Register ({\tt mstatus})} -The {\tt mstatus} register is an M-XLEN-bit read/write register +The {\tt mstatus} register is an MXLEN-bit read/write register formatted as shown in Figure~\ref{mstatusreg-rv32} for RV32 and Figure~\ref{mstatusreg} for RV64 and RV128. The {\tt mstatus} register keeps track of and controls the hart's current operating @@ -590,21 +590,21 @@ For RV64 and RV128 systems, the SXL and UXL fields are \warl\ fields that control the value of XLEN for S-mode and U-mode, respectively. The encoding of these fields is the same as the MXL field of {\tt misa}, shown in Table~\ref{misabase}. The effective -XLEN in S-mode and U-mode are termed {\em S-XLEN} and {\em U-XLEN}, +XLEN in S-mode and U-mode are termed {\em SXLEN} and {\em UXLEN}, respectively. For RV32 systems, the SXL and UXL fields do not exist, and -S-XLEN~=~32 and U-XLEN~=~32. +SXLEN=32 and UXLEN=32. For RV64 and RV128 systems, if S-mode is not supported, then SXL is hardwired to zero. Otherwise, it is a \warl\ field that encodes the current value of -S-XLEN. In particular, the implementation may hardwire SXL so that -S-XLEN~=~M-XLEN. +SXLEN. In particular, the implementation may hardwire SXL so that +SXLEN=MXLEN. For RV64 and RV128 systems, if U-mode is not supported, then UXL is hardwired to zero. Otherwise, it is a \warl\ field that encodes the current value of -U-XLEN. In particular, the implementation may hardwire UXL so that -U-XLEN~=~M-XLEN or U-XLEN~=~S-XLEN. +UXLEN. In particular, the implementation may hardwire UXL so that +UXLEN=MXLEN or UXLEN=SXLEN. Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register @@ -619,9 +619,9 @@ always be an error, but machine operation is well-defined even in this case. \end{commentary} -If M-XLEN is changed from 32 to a wider width, each of {\tt mstatus} fields SXL and +If MXLEN is changed from 32 to a wider width, each of {\tt mstatus} fields SXL and UXL, if not hardwired to a forced value, gets the value corresponding to the -widest supported width not wider than the new M-XLEN. +widest supported width not wider than the new MXLEN. \subsection{Memory Privilege in {\tt mstatus} Register} @@ -947,7 +947,7 @@ interrupts, unless the interrupt results in a user-level context swap. \subsection{Machine Trap-Vector Base-Address Register ({\tt mtvec})} -The {\tt mtvec} register is an M-XLEN-bit read/write register that holds +The {\tt mtvec} register is an MXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). @@ -1008,7 +1008,7 @@ the BASE field plus four times the interrupt cause number. For example, a machine-mode timer interrupt (see Table~\ref{mcauses}) causes the {\tt pc} to be set to BASE+{\tt 0x1c}. Setting MODE=Vectored may impose an additional alignment constraint on BASE, -requiring up to $4\times$M-XLEN-byte alignment. +requiring up to $4\times$MXLEN-byte alignment. \begin{commentary} When vectored interrupts are enabled, interrupt cause 0, which corresponds to @@ -1032,7 +1032,7 @@ read/write bits within {\tt medeleg} and {\tt mideleg} to indicate that certain exceptions and interrupts should be processed directly by a lower privilege level. The machine exception delegation register ({\tt medeleg}) and machine interrupt delegation register ({\tt - mideleg}) are M-XLEN-bit read/write registers. + mideleg}) are MXLEN-bit read/write registers. In systems with all three privilege modes (M/S/U), setting a bit in {\tt medeleg} or {\tt mideleg} will delegate the corresponding trap in @@ -1132,9 +1132,9 @@ Some exceptions cannot occur at less privileged modes, and corresponding \subsection{Machine Interrupt Registers ({\tt mip} and {\tt mie})} -The {\tt mip} register is an M-XLEN-bit read/write register containing +The {\tt mip} register is an MXLEN-bit read/write register containing information on pending interrupts, while {\tt mie} is the -corresponding M-XLEN-bit read/write register containing interrupt enable +corresponding MXLEN-bit read/write register containing interrupt enable bits. Only the bits corresponding to lower-privilege software interrupts (USIP, SSIP), timer interrupts (UTIP, STIP), and external interrupts (UEIP, SEIP) in {\tt mip} @@ -1483,7 +1483,7 @@ all RV32, RV64, and RV128 systems. The hardware performance monitor includes 29 additional 64-bit event counters, {\tt mhpmcounter3}--{\tt mhpmcounter31}. The event selector CSRs, {\tt -mhpmevent3}--{\tt mhpmevent31}, are M-XLEN-bit \warl\ registers that control which event +mhpmevent3}--{\tt mhpmevent31}, are MXLEN-bit \warl\ registers that control which event causes the corresponding counter to increment. The meaning of these events is defined by the platform, but event 0 is reserved to mean ``no event.'' All counters should be implemented, but a legal implementation is to hard-wire @@ -1635,7 +1635,7 @@ and emulate this functionality in M-mode software. \subsection{Machine Scratch Register ({\tt mscratch})} -The {\tt mscratch} register is an M-XLEN-bit read/write register +The {\tt mscratch} register is an MXLEN-bit read/write register dedicated for use by machine mode. Typically, it is used to hold a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler. @@ -1676,7 +1676,7 @@ Unlike the MIPS design, the OS can rely on holding a value in the {\tt \subsection{Machine Exception Program Counter ({\tt mepc})} -{\tt mepc} is an M-XLEN-bit read/write register formatted as shown in +{\tt mepc} is an MXLEN-bit read/write register formatted as shown in Figure~\ref{mepcreg}. The low bit of {\tt mepc} ({\tt mepc[0]}) is always zero. On implementations that support only IALIGN=32, the two low bits ({\tt mepc[1:0]}) are always zero. @@ -1716,7 +1716,7 @@ MXLEN \\ \subsection{Machine Cause Register ({\tt mcause})} -The {\tt mcause} register is an M-XLEN-bit read-write register formatted as +The {\tt mcause} register is an MXLEN-bit read-write register formatted as shown in Figure~\ref{mcausereg}. When a trap is taken into M-mode, {\tt mcause} is written with a code indicating the event that caused the trap. Otherwise, {\tt mcause} is never written by the implementation, though it may be @@ -1812,7 +1812,7 @@ vector table. \subsection{Machine Trap Value ({\tt mtval}) Register} -The {\tt mtval} register is an M-XLEN-bit read-write register formatted as shown +The {\tt mtval} register is an MXLEN-bit read-write register formatted as shown in Figure~\ref{mtvalreg}. When a trap is taken into M-mode, {\tt mtval} is either set to zero or written with exception-specific information to assist software in handling the trap. Otherwise, {\tt mtval} is never written by the @@ -2550,7 +2550,7 @@ PMP violations are always trapped precisely at the processor. \subsection{Physical Memory Protection CSRs} -PMP entries are described by an 8-bit configuration register and one M-XLEN-bit +PMP entries are described by an 8-bit configuration register and one MXLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 16 PMP entries are supported. If any PMP entries are implemented, then all PMP CSRs must be implemented, @@ -2567,7 +2567,7 @@ Figure~\ref{pmpcfg-rv64}; {\tt pmpcfg1} and {\tt pmpcfg3} are illegal. \begin{commentary} RV64 systems use {\tt pmpcfg2}, rather than {\tt pmpcfg1}, to hold configurations for PMP entries 8--15. This design reduces the cost of -supporting multiple M-XLEN values, since the configurations for PMP +supporting multiple MXLEN values, since the configurations for PMP entries 8--11 appear in {\tt pmpcfg2}[31:0] for both RV32 and RV64. \end{commentary} diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index 3dc2613..1603185 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -439,7 +439,7 @@ value is written. \section{CSR Width Modulation} -If the width of a CSR is changed (for example, by changing M-XLEN or U-XLEN, as +If the width of a CSR is changed (for example, by changing MXLEN or UXLEN, as described in Section~\ref{xlen-control}), the values of the {\em writable} fields and bits of the new-width CSR are, unless specified otherwise, determined from the previous-width CSR as though by this algorithm: diff --git a/src/supervisor.tex b/src/supervisor.tex index e0f4c3d..de6656b 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -36,7 +36,7 @@ the supervisor-level CSR descriptions. \label{sstatus} -The {\tt sstatus} register is an S-XLEN-bit read/write register +The {\tt sstatus} register is an SXLEN-bit read/write register formatted as shown in Figure~\ref{sstatusreg-rv32} for RV32 and Figure~\ref{sstatusreg} for RV64 and RV128. The {\tt sstatus} register keeps track of the processor's current operating state. @@ -184,16 +184,16 @@ sstatus} is equivalent to reading or writing the homonymous field in \subsection{Base ISA Control in {\tt sstatus} Register} -The UXL field controls the value of XLEN for U-mode, termed {\em U-XLEN}, -which may differ from the value of XLEN for S-mode, termed {\em S-XLEN}. The +The UXL field controls the value of XLEN for U-mode, termed {\em UXLEN}, +which may differ from the value of XLEN for S-mode, termed {\em SXLEN}. The encoding of UXL is the same as that of the MXL field of {\tt misa}, shown in Table~\ref{misabase}. -For RV32 systems, the UXL field does not exist, and U-XLEN~=~32. For RV64 and -RV128 systems, it is a \warl\ field that encodes the current value of U-XLEN. -In particular, the implementation may hardwire UXL so that U-XLEN~=~S-XLEN. +For RV32 systems, the UXL field does not exist, and UXLEN=32. For RV64 and +RV128 systems, it is a \warl\ field that encodes the current value of UXLEN. +In particular, the implementation may hardwire UXL so that UXLEN=SXLEN. -If U-XLEN~$\ne$~S-XLEN, instructions executed in the narrower mode must ignore +If UXLEN~$\ne$~SXLEN, instructions executed in the narrower mode must ignore source register operand bits above the configured XLEN, and must sign-extend results to fill the widest supported XLEN in the destination register. @@ -238,7 +238,7 @@ alternate mapping. \subsection{Supervisor Trap Vector Base Address Register ({\tt stvec})} -The {\tt stvec} register is an S-XLEN-bit read/write register that holds +The {\tt stvec} register is an SXLEN-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE). @@ -292,7 +292,7 @@ the BASE field plus four times the interrupt cause number. For example, a supervisor-mode timer interrupt (see Table~\ref{scauses}) causes the {\tt pc} to be set to BASE+{\tt 0x14}. Setting MODE=Vectored may impose an additional alignment constraint on BASE, -requiring up to $4\times$S-XLEN-byte alignment. +requiring up to $4\times$SXLEN-byte alignment. \begin{commentary} When vectored interrupts are enabled, interrupt cause 0, which corresponds to @@ -304,9 +304,9 @@ or delegated to user mode. \subsection{Supervisor Interrupt Registers ({\tt sip} and {\tt sie})} -The {\tt sip} register is an S-XLEN-bit read/write register containing +The {\tt sip} register is an SXLEN-bit read/write register containing information on pending interrupts, while {\tt sie} is the corresponding -S-XLEN-bit read/write register containing interrupt enable bits. +SXLEN-bit read/write register containing interrupt enable bits. \begin{figure*}[h!] {\footnotesize @@ -510,7 +510,7 @@ Hence, they are effectively \warl\ fields. \subsection{Supervisor Scratch Register ({\tt sscratch})} -The {\tt sscratch} register is an S-XLEN-bit read/write register, +The {\tt sscratch} register is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, {\tt sscratch} is used to hold a pointer to the hart-local supervisor context while the hart is executing user code. At the beginning of a trap handler, {\tt @@ -536,7 +536,7 @@ SXLEN \\ \subsection{Supervisor Exception Program Counter ({\tt sepc})} -{\tt sepc} is an S-XLEN-bit read/write register formatted as shown in +{\tt sepc} is an SXLEN-bit read/write register formatted as shown in Figure~\ref{epcreg}. The low bit of {\tt sepc} ({\tt sepc[0]}) is always zero. On implementations that support only IALIGN=32, the two low bits ({\tt sepc[1:0]}) are always zero. @@ -576,7 +576,7 @@ SXLEN \\ \subsection{Supervisor Cause Register ({\tt scause})} -The {\tt scause} register is an S-XLEN-bit read-write register formatted as +The {\tt scause} register is an SXLEN-bit read-write register formatted as shown in Figure~\ref{scausereg}. When a trap is taken into S-mode, {\tt scause} is written with a code indicating the event that caused the trap. Otherwise, {\tt scause} is never written by the implementation, though it may be @@ -648,7 +648,7 @@ so is only guaranteed to hold supported exception codes. \subsection{Supervisor Trap Value ({\tt stval}) Register} -The {\tt stval} register is an S-XLEN-bit read-write register formatted as shown +The {\tt stval} register is an SXLEN-bit read-write register formatted as shown in Figure~\ref{stvalreg}. When a trap is taken into S-mode, {\tt stval} is written with exception-specific information to assist software in handling the trap. Otherwise, {\tt stval} is never written by the implementation, though @@ -719,8 +719,8 @@ smaller of XLEN and the width of the longest supported instruction. \subsection{Supervisor Address Translation and Protection ({\tt satp}) Register} \label{sec:satp} -The {\tt satp} register is an S-XLEN-bit read/write register, formatted as shown -in Figure~\ref{rv32satp} for S-XLEN~=~32 and Figure~\ref{rv64satp} for S-XLEN~=~64, which +The {\tt satp} register is an SXLEN-bit read/write register, formatted as shown +in Figure~\ref{rv32satp} for SXLEN=32 and Figure~\ref{rv64satp} for SXLEN=64, which controls supervisor-mode address translation and protection. This register holds the physical page number (PPN) of the root page table, i.e., its supervisor physical address divided by \wunits{4}{KiB}; @@ -964,7 +964,7 @@ SFENCE.VMA depends on {\em rs1} and {\em rs2} as follows: Accesses to global mappings are not ordered. \end{itemize} -When {\em rs2}$\neq${\tt x0}, bits S-XLEN-1:ASIDMAX of the value held in {\em +When {\em rs2}$\neq${\tt x0}, bits SXLEN-1:ASIDMAX of the value held in {\em rs2} are reserved for future use and should be zeroed by software and ignored by current implementations. Furthermore, if ASIDLEN~$<$~ASIDMAX, the implementation shall ignore bits ASIDMAX-1:ASIDLEN of the value held in {\em |