diff options
-rw-r--r-- | src/d.tex | 3 | ||||
-rw-r--r-- | src/f.tex | 3 | ||||
-rw-r--r-- | src/q.tex | 3 |
3 files changed, 9 insertions, 0 deletions
@@ -148,6 +148,9 @@ offset[11:5] & src & base & D & offset[4:0] & STORE-FP \\ FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN$\geq$64. +FLD and FSD do not modify the bits being transferred; in particular, the +payloads of non-canonical NaNs are preserved. + \section{Double-Precision Floating-Point Computational Instructions} The double-precision floating-point computational instructions are @@ -363,6 +363,9 @@ offset[11:5] & src & base & W & offset[4:0] & STORE-FP \\ FLW and FSW are only guaranteed to execute atomically if the effective address is naturally aligned. +FLW and FSW do not modify the bits being transferred; in particular, the +payloads of non-canonical NaNs are preserved. + \section{Single-Precision Floating-Point Computational Instructions} \label{sec:single-float-compute} @@ -64,6 +64,9 @@ offset[11:5] & src & base & Q & offset[4:0] & STORE-FP \\ FLQ and FSQ are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN=128. +FLQ and FSQ do not modify the bits being transferred; in particular, the +payloads of non-canonical NaNs are preserved. + \section{Quad-Precision Computational Instructions} A new supported format is added to the format field of most |