diff options
| -rw-r--r-- | src/preface.tex | 27 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 2 |
2 files changed, 12 insertions, 17 deletions
diff --git a/src/preface.tex b/src/preface.tex index 164b814..0410047 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -1,19 +1,17 @@ \chapter{Preface} -This is {\bf a draft of} the next release of the document describing -the RISC-V unprivileged architecture, targeted for release \specrev. -This release will be used in ratifying the base and standard +This document describes the RISC-V unprivileged architecture. This +release \specrev\ will be used in ratifying the base and standard extensions described below. -The document contains the following versions of the RISC-V ISA -modules: - The RISC-V RVWMO memory model has been ratified at this time. The ISA modules marked {\bf Ratification} are scheduled for ratification with this release of the specification. The modules marked {\em Frozen} are not expected to change before being put up for ratification. The modules marked {\em Draft} are expected to change before ratification. +The document contains the following versions of the RISC-V ISA +modules: { \begin{table}[hbt] @@ -53,7 +51,8 @@ modules marked {\em Draft} are expected to change before ratification. \end{table} } -The major changes in this version of the document include: +The changes in this version of the document include: +\vspace{-0.2in} \begin{itemize} \parskip 0pt \itemsep 1pt @@ -77,16 +76,12 @@ The major changes in this version of the document include: non-conforming}. \item Removed text implying operation under alternate endianness, as alternate-endianness operation has not yet been defined for RISC-V. -\item Changed description of misaligned load and store behavior to - reflect that this is now an unprivileged ISA manual, not a user - ISA manual. The specification now allows visible misaligned address - traps in execution environment interfaces, rather than just mandating +\item Changed description of misaligned load and store behavior. The + specification now allows visible misaligned address traps in + execution environment interfaces, rather than just mandating invisible handling of misaligned loads and stores in user mode. - This behavior was already needed to support the definition of the - classic privileged architecture. Also, now allow access exceptions - to be reported for misaligned access that should not be emulated. - The same ability to report access exceptions instead of misaligned - exceptions was added for atomic operations also. + Also, now allows access exceptions to be reported for misaligned + accesses (including atomics) that should not be emulated. \item Moved FENCE.I out of the mandatory base and into a separate extension, with Zifencei ISA name. FENCE.I was removed from the Linux user ABI and is problematic in implementations with large incoherent instruction and diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index 998b8c5..c19b368 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -6,7 +6,7 @@ \input{preamble} -\newcommand{\specrev}{20181105-draft} +\newcommand{\specrev}{\mbox{20181106-Base-Ratification}} \begin{document} |