diff options
| -rw-r--r-- | src/d.tex | 8 | ||||
| -rw-r--r-- | src/f.tex | 11 | ||||
| -rw-r--r-- | src/preface.tex | 5 | ||||
| -rw-r--r-- | src/q.tex | 9 |
4 files changed, 18 insertions, 15 deletions
@@ -18,8 +18,6 @@ as described below in Section~\ref{nanboxing}. FLEN can be 32, 64, or 128 depending on which of the F, D, and Q extensions are supported. There can be up to four different floating-point precisions supported, including H, F, D, and Q. -Half-precision H scalar values are only supported if the V vector -extension is supported. \end{commentary} \section{NaN Boxing of Narrower Values} @@ -222,7 +220,7 @@ number in floating-point register {\em rd}. FCVT.WU.D, FCVT.LU.D, FCVT.D.WU, and FCVT.D.LU variants convert to or from unsigned integer values. For RV64, FCVT.W[U].D sign-extends the 32-bit result. -FCVT.L[U].D and FCVT.D.L[U] are illegal in RV32. +FCVT.L[U].D and FCVT.D.L[U] are RV64-only instructions. The range of valid inputs for FCVT.{\em int}.D and the behavior for invalid inputs are the same as for FCVT.{\em int}.S. @@ -319,8 +317,8 @@ FSGNJ & D & src2 & src1 & J[N]/JX & dest & OP-FP \\ \end{tabular} \end{center} -For RV64 only, instructions are provided to move bit patterns between -the floating-point and integer registers. FMV.X.D moves the +For XLEN$>=$64 only, instructions are provided to move bit patterns +between the floating-point and integer registers. FMV.X.D moves the double-precision value in floating-point register {\em rs1} to a representation in IEEE 754-2008 standard encoding in integer register {\em rd}. FMV.D.X moves the double-precision value encoded in IEEE @@ -157,8 +157,8 @@ instruction, or a dynamic rounding mode held in {\tt frm}. Rounding modes are encoded as shown in Table~\ref{rm}. A value of 111 in the instruction's {\em rm} field selects the dynamic rounding mode held in {\tt frm}. If {\tt frm} is set to an invalid value (101--111), any subsequent attempt to execute -a floating-point operation with a dynamic rounding mode will cause an illegal -instruction trap. Some instructions that have the {\em rm} field are +a floating-point operation with a dynamic rounding mode will raise an illegal +instruction exception. Some instructions that have the {\em rm} field are nevertheless unaffected by the rounding mode; they should have their {\em rm} field set to RNE (000). @@ -390,7 +390,7 @@ Meaning \\ \hline 00 & S & 32-bit single-precision \\ 01 & D & 64-bit double-precision \\ -10 & - & {\em reserved} \\ +10 & H & 16-bit half-precision \\ 11 & Q & 128-bit quad-precision \\ \hline \end{tabular} @@ -502,8 +502,9 @@ respectively, in integer register {\em rs1} into a floating-point number in floating-point register {\em rd}. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and FCVT.S.LU variants convert to or from unsigned integer values. -For RV64, FCVT.W[U].S sign-extends the 32-bit result. -FCVT.L[U].S and FCVT.S.L[U] are illegal in RV32. +For XLEN$>32$, FCVT.W[U].S sign-extends the 32-bit result to the +destination register width. +FCVT.L[U].S and FCVT.S.L[U] are RV64-only instructions. If the rounded result is not representable in the destination format, it is clipped to the nearest value and the invalid flag is set. Table~\ref{tab:int_conv} gives the range of valid inputs for FCVT.{\em int}.S diff --git a/src/preface.tex b/src/preface.tex index 06cb435..a7e0111 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -67,7 +67,10 @@ The major changes in this version of the document include: produced illegal instruction exceptions in RV32E and RV64I chapters. \item Counter/timer instructions are now not considered part of mandatory base ISA, and so CSR instructions were moved into separate - chapter, with the unprivileged counters into another separate chapter. + chapter, with the unprivileged counters into another separate + chapter. +\item Explicitly defined the 16-bit half-precision floating-point + format for floating-point instructions in the 2-bit {\em fmt field.} \item Defined the signed-zero behavior of FMIN.{\em fmt} and FMAX.{\em fmt}, and changed their behavior on signaling-NaN inputs to conform to the minimumNumber and maximumNumber operations in the proposed IEEE 754-201x @@ -79,7 +79,7 @@ Meaning \\ \hline 00 & S & 32-bit single-precision \\ 01 & D & 64-bit double-precision \\ -10 & - & {\em reserved} \\ +10 & H & 16-bit half-precision \\ 11 & Q & 128-bit quad-precision \\ \hline \end{tabular} @@ -233,11 +233,12 @@ FSGNJ & Q & src2 & src1 & J[N]/JX & dest & OP-FP \\ \end{tabular} \end{center} -FMV.X.Q and FMV.Q.X instructions are not provided, so quad-precision bit -patterns must be moved to the integer registers via memory. +FMV.X.Q and FMV.Q.X instructions are not provided in RV32 or RV64, so +quad-precision bit patterns must be moved to the integer registers via +memory. \begin{commentary} -RV128 supports FMV.X.Q and FMV.Q.X in the Q extension. +RV128 will spuport FMV.X.Q and FMV.Q.X in the Q extension. \end{commentary} \section{Quad-Precision Floating-Point Compare Instructions} |