diff options
| -rw-r--r-- | src/j.tex | 13 | ||||
| -rw-r--r-- | src/machine.tex | 2 | ||||
| -rw-r--r-- | src/naming.tex | 1 | ||||
| -rw-r--r-- | src/preface.tex | 1 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 1 | ||||
| -rw-r--r-- | src/t.tex | 2 |
6 files changed, 18 insertions, 2 deletions
diff --git a/src/j.tex b/src/j.tex new file mode 100644 index 0000000..37a8b37 --- /dev/null +++ b/src/j.tex @@ -0,0 +1,13 @@ +\chapter{``J'' Standard Extension for Dynamically Translated Languages, Version 0.0} +\label{sec:j} + +This chapter is a placeholder for a future standard extension to +support dynamically translated languages. + +\begin{commentary} + Many popular languages are usually implemented via dynamic + translation, including Java and Javascript. These languages can + benefit from additional ISA support for dynamic checks and garbage + collection. +\end{commentary} + diff --git a/src/machine.tex b/src/machine.tex index 739c254..48a99d8 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -114,7 +114,7 @@ Bit & Character & Description \\ 6 & G & Additional standard extensions present \\ 7 & H & Hypervisor mode implemented \\ 8 & I & RV32I/64I/128I base ISA \\ - 9 & J & {\em Reserved} \\ + 9 & J & {\em Tentatively reserved for Dynamically Translated Languages extension} \\ 10 & K & {\em Reserved} \\ 11 & L & {\em Tentatively reserved for Decimal Floating-Point extension} \\ 12 & M & Integer Multiply/Divide extension \\ diff --git a/src/naming.tex b/src/naming.tex index ac649f2..6fa17b3 100644 --- a/src/naming.tex +++ b/src/naming.tex @@ -112,6 +112,7 @@ Quad-Precision Floating-Point & Q \\ Decimal Floating-Point & L \\ 16-bit Compressed Instructions & C \\ Bit Manipulation & B \\ +Dynamic Languages & J \\ Transactional Memory & T \\ Packed-SIMD Extensions & P \\ Vector Extensions & V \\ diff --git a/src/preface.tex b/src/preface.tex index 573fa01..73be621 100644 --- a/src/preface.tex +++ b/src/preface.tex @@ -25,6 +25,7 @@ versions of the RISC-V ISA modules: C & 1.9 & N \\ V & 0.1 & N \\ B & 0.0 & N \\ + J & 0.0 & N \\ T & 0.0 & N \\ P & 0.1 & N \\ \hline diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index 91641f9..3285172 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -59,6 +59,7 @@ International License. \input{c} \input{v} \input{b} +\input{j} \input{t} \input{p} \input{rv128} @@ -1,5 +1,5 @@ \chapter{``T'' Standard Extension for Transactional Memory, Version 0.0} -\label{sec:bits} +\label{sec:tm} This chapter is a placeholder for a future standard extension to provide transactional memory operations. |