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| -rw-r--r-- | src/csr.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/csr.tex b/src/csr.tex index f73a8cd..16d8e6f 100644 --- a/src/csr.tex +++ b/src/csr.tex @@ -182,7 +182,7 @@ scheme. \begin{commentary} These CSR-ordering constraints are imposed primarily to support ordering -memory and memory-mapped I/O accesses with respect to reads of the {\tt time} +main memory and memory-mapped I/O accesses with respect to reads of the {\tt time} CSR. With the exception of the {\tt time}, {\tt cycle}, and {\tt mcycle} CSRs, the CSRs defined thus far in Volumes I and II of this specification are not directly accessible to other harts or devices and cause no side effects |