diff options
| -rw-r--r-- | src/a.tex | 8 | ||||
| -rw-r--r-- | src/machine.tex | 32 | ||||
| -rw-r--r-- | src/rv32.tex | 2 | ||||
| -rw-r--r-- | src/supervisor.tex | 14 |
4 files changed, 28 insertions, 28 deletions
@@ -137,8 +137,8 @@ defined in future versions or extensions to the ISA. For LR and SC, the A extension requires that the address held in {\em rs1} be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit -words). If the address is not naturally aligned, a misaligned address -exception or an access exception will be generated. The access +words). If the address is not naturally aligned, an address-misaligned +exception or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. @@ -326,8 +326,8 @@ sign-extend the value placed in {\em rd}. For AMOs, the A extension requires that the address held in {\em rs1} be naturally aligned to the size of the operand (i.e., eight-byte aligned for 64-bit words and four-byte aligned for 32-bit words). If -the address is not naturally aligned, a misaligned address exception -or an access exception will be generated. The access exception can be +the address is not naturally aligned, an address-misaligned exception +or an access-fault exception will be generated. The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated. The ``Zam'' extension, described in Chapter~\ref{sec:zam}, diff --git a/src/machine.tex b/src/machine.tex index 271087d..343da1d 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -713,7 +713,7 @@ not supported. \begin{commentary} The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entries. In particular, they have no impact on whether -access exceptions are raised due to PMAs or PMP. +access-fault exceptions are raised due to PMAs or PMP. \end{commentary} \subsubsection{Endianness Control in {\tt mstatus} and {\tt mstatush} Registers} @@ -2133,8 +2133,8 @@ implementation, though it may be explicitly written by software. The hardware platform will specify which exceptions must set {\tt mtval} informatively and which may unconditionally set it to zero. -When a hardware breakpoint is triggered, or an instruction-fetch, load, or -store address-misaligned, access, or page-fault exception occurs, {\tt +When a hardware breakpoint is triggered, or an instruction, load, or +store address-misaligned, access-fault, or page-fault exception occurs, {\tt mtval} is written with the faulting virtual address. On an illegal instruction trap, {\tt mtval} may be written with the first XLEN or ILEN bits of the faulting instruction as described below. For other traps, @@ -2152,7 +2152,7 @@ bits of the faulting instruction as described below. For other traps, \end{commentary} \begin{commentary} When page-based virtual memory is enabled, {\tt mtval} is written with - the faulting virtual address, even for physical-memory access exceptions. + the faulting virtual address, even for physical-memory access-fault exceptions. This design reduces datapath cost for most implementations, particularly those with hardware page-table walkers. \end{commentary} @@ -2174,9 +2174,9 @@ MXLEN \\ \label{mtvalreg} \end{figure} -For misaligned loads and stores that cause access or page-fault exceptions, +For misaligned loads and stores that cause access-fault or page-fault exceptions, {\tt mtval} will contain the virtual address of the portion of the access that -caused the fault. For instruction-fetch access or page-fault exceptions on +caused the fault. For instruction access-fault or page-fault exceptions on systems with variable-length instructions, {\tt mtval} will contain the virtual address of the portion of the instruction that caused the fault while {\tt mepc} will point to the beginning of the instruction. @@ -2549,7 +2549,7 @@ memory, including accesses that have undergone virtual to physical memory translation. To aid in system debugging, we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks. Precisely trapped PMA violations manifest -as load, store, or instruction-fetch access exceptions, distinct from +as instruction, load, or store access-fault exceptions, distinct from virtual-memory page-fault exceptions. Precise PMA traps might not always be possible, for example, when probing a legacy bus architecture that uses access failures as part of the discovery mechanism. In this @@ -2680,10 +2680,10 @@ and stores uses the same mutex, all accesses to a given address that use the same word size will be mutually atomic. \end{commentary} -Implementations may raise access exceptions instead of address-misaligned +Implementations may raise access-fault exceptions instead of address-misaligned exceptions for some misaligned accesses, indicating the instruction should not be emulated by a trap handler. If, for a given address and access width, all -misaligned LRs/SCs and AMOs generate access exceptions, then regular +misaligned LRs/SCs and AMOs generate access-fault exceptions, then regular misaligned loads and stores using the same address and access width are not required to execute atomically. @@ -2841,7 +2841,7 @@ generate spurious accesses to non-idempotent memory regions. \begin{commentary} Non-idempotent regions might not support misaligned accesses. Misaligned -accesses to such regions should raise access exceptions rather than +accesses to such regions should raise access-fault exceptions rather than address-misaligned exceptions, indicating that software should not emulate the misaligned access using multiple smaller accesses, which could cause unexpected side effects. @@ -3107,12 +3107,12 @@ described in the following sections. \end{figure} Attempting to fetch an instruction from a PMP region that does not have execute -permissions raises a fetch access exception. Attempting to execute +permissions raises an instruction access-fault exception. Attempting to execute a load or load-reserved instruction whose effective address lies within -a PMP region without read permissions raises a load access exception. +a PMP region without read permissions raises a load access-fault exception. Attempting to execute a store, store-conditional (regardless of success), or AMO instruction whose effective address lies within a PMP region without -write permissions raises a store access exception. +write permissions raises a store access-fault exception. If MXLEN is changed, the contents of the {\tt pmp{\em x}cfg} fields are preserved, but appear in the {\tt pmpcfg{\em y}} CSR prescribed by the new @@ -3243,16 +3243,16 @@ If at least one PMP entry is implemented, but all PMP entries' A fields are set to OFF, then all S-mode and U-mode memory accesses will fail. \end{commentary} -Failed accesses generate a load, store, or instruction access exception. Note +Failed accesses generate an instruction, load, or store access-fault exception. Note that a single instruction may generate multiple accesses, which may not be -mutually atomic. An access exception is generated if at least one access +mutually atomic. An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects. Notably, instructions that reference virtual memory are decomposed into multiple accesses. On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an -access exception occurs. In particular, a portion of a misaligned store +access-fault exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check. The same behavior may manifest for floating-point stores wider than XLEN bits (e.g., the FSD instruction in RV32D), even when the store diff --git a/src/rv32.tex b/src/rv32.tex index ee35e64..ba8e169 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1070,7 +1070,7 @@ An EEI may not guarantee misaligned loads and stores are handled invisibly. In this case, loads and stores that are not naturally aligned may either complete execution successfully or raise an exception. The exception raised can be either an address-misaligned -exception or an access exception. For a memory access that would +exception or an access-fault exception. For a memory access that would otherwise be able to complete except for the misalignment, an access exception can be raised instead of an address-misaligned exception if the misaligned access should not be emulated, e.g., if accesses to the diff --git a/src/supervisor.tex b/src/supervisor.tex index ba29386..ba3ced5 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -639,8 +639,8 @@ which exceptions must set {\tt stval} informatively and which may unconditionally set it to zero. -When a hardware breakpoint is triggered, or an instruction-fetch, load, or -store address-misaligned, access, or page-fault exception occurs, {\tt stval} +When a hardware breakpoint is triggered, or an instruction, load, or +store address-misaligned, access-fault, or page-fault exception occurs, {\tt stval} is written with the faulting virtual address. On an illegal instruction trap, {\tt stval} may be written with the first XLEN or ILEN bits of the faulting instruction as described below. For other exceptions, {\tt stval} is set to @@ -664,10 +664,10 @@ SXLEN \\ \label{stvalreg} \end{figure} -For misaligned loads and stores that cause access or page-fault +For misaligned loads and stores that cause access-fault or page-fault exceptions, {\tt stval} will contain the virtual address of the portion of the access that caused the fault. For -instruction-fetch access or page-fault exceptions on systems +instruction access-fault or page-fault exceptions on systems with variable-length instructions, {\tt stval} will contain the virtual address of the portion of the instruction that caused the fault while {\tt sepc} will point to the beginning of the @@ -1015,7 +1015,7 @@ should be set to the ASID for which the translation is being modified. changing an invalid PTE to a valid leaf, software may choose to execute the SFENCE.VMA lazily. After modifying the PTE but before executing SFENCE.VMA, either the new or old permissions will be used. In the latter -case, a page fault exception might occur, at which point software should +case, a page-fault exception might occur, at which point software should execute SFENCE.VMA in accordance with the previous bullet point. \end{itemize} @@ -1297,7 +1297,7 @@ follows: \item Let $pte$ be the value of the PTE at address $a+va.vpn[i]\times \textrm{PTESIZE}$. (For Sv32, PTESIZE=4.) If accessing $pte$ violates a PMA or PMP check, raise an - access exception corresponding to the original access type. + access-fault exception corresponding to the original access type. \item If $pte.v=0$, or if $pte.r=0$ and $pte.w=1$, stop and raise a page-fault exception corresponding to the original access type. @@ -1323,7 +1323,7 @@ follows: \begin{itemize} \item Set $pte.a$ to 1 and, if the memory access is a store, also set $pte.d$ to 1. - \item If this access violates a PMA or PMP check, raise an access exception + \item If this access violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type. \item This update and the loading of $pte$ in step 2 must be atomic; in particular, no intervening store to the PTE may be perceived to have |