diff options
| -rw-r--r-- | src/counters.tex | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/counters.tex b/src/counters.tex index adc8e0c..65c95b7 100644 --- a/src/counters.tex +++ b/src/counters.tex @@ -182,3 +182,24 @@ values atomically, but this would increase the size of the user context, especially for implementations with a richer set of counters. \end{commentary} +\section{Hardware Performance Counters} + +There is CSR space allocated for 29 additional unprivileged 64-bit +hardware performance counters, {\tt hpmcounter3}--{\tt hpmcounter31}. +For RV32, the upper 32 bits of these performance counters is +accessible via additional CSRs {\tt hpmcounter3h}--{\tt + hpmcounter31h}. These counters count platform-specific events and +are configured via additional privileged registers. The number and +width of these additional counters, and the set of events they count +is platform-specific. + +\begin{commentary} + The privileged architecture manual describes the privileged CSRs + controlling access to these counters and to set the events to be + counted. + + It would be useful to eventually standardize event settings to count + ISA-level metrics, such as the number of floating-point instructions + executed for example, and possibly a few common microarchitectural + metrics, such as ``L1 instruction cache misses''. +\end{commentary} |