diff options
| -rw-r--r-- | src/priv-preface.tex | 3 | ||||
| -rw-r--r-- | src/supervisor.tex | 158 |
2 files changed, 140 insertions, 21 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index b16b0dd..34b4124 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -15,6 +15,7 @@ modules: \em Machine ISA & \em 1.12 & \em Draft \\ \em Supervisor ISA & \em 1.12 & \em Draft \\ \em Svnapot Extension & \em 0.1 & \em Draft \\ + \em Svpbmt Extension & \em 0.1 & \em Draft \\ \em Hypervisor ISA & \em 0.6 & \em Draft \\ \em N Extension & \em 1.1 & \em Draft \\ \hline @@ -68,6 +69,8 @@ Additionally, the following compatible changes have been made since version \item An additional 48 optional PMP registers have been defined. \item Added the Svnapot Standard Extension draft, along with the N bit in Sv39, Sv48, and Sv57 PTEs +\item Added the Svpbmt Standard Extension draft, along with the PBMT bits + in Sv39, Sv48, and Sv57 PTEs. \item Described the behavior of address-translation caches a little more explicitly. \item Slightly relaxed the atomicity requirement for A and D bit updates diff --git a/src/supervisor.tex b/src/supervisor.tex index 6830174..93c833c 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1764,9 +1764,10 @@ quickly distinguish user and supervisor address regions. \begin{figure*}[h!] {\footnotesize \begin{center} -\begin{tabular}{cY@{}Y@{}Y@{}Y@{}Fcccccccc} +\begin{tabular}{cF@{}Y@{}Y@{}Y@{}Y@{}Fcccccccc} \instbit{63} & -\instbitrange{62}{54} & +\instbitrange{62}{61} & +\instbitrange{60}{54} & \instbitrange{53}{28} & \instbitrange{27}{19} & \instbitrange{18}{10} & @@ -1781,6 +1782,7 @@ quickly distinguish user and supervisor address regions. \instbit{0} \\ \hline \multicolumn{1}{|c|}{N} & +\multicolumn{1}{c|}{PBMT} & \multicolumn{1}{c|}{\it Reserved} & \multicolumn{1}{c|}{PPN[2]} & \multicolumn{1}{c|}{PPN[1]} & @@ -1795,7 +1797,7 @@ quickly distinguish user and supervisor address regions. \multicolumn{1}{c|}{R} & \multicolumn{1}{c|}{V} \\ \hline -1 & 9 & 26 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ +1 & 2 & 7 & 26 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ \end{tabular} \end{center} } @@ -1812,8 +1814,9 @@ root page table is stored in the {\tt satp} register's PPN field. The PTE format for Sv39 is shown in Figure~\ref{sv39pte}. Bits 9--0 have the same meaning as for Sv32. -Bit 63 is reserved for use by the Svnapot extension in -Chapter~\ref{svnapot}. Bits 62--54 are reserved for future standard use. All +Bit 63 is reserved for use by the Svnapot extension in Chapter~\ref{svnapot}. +Bits 62--61 are reserved for use by the Svpbmt extension in +Chapter~\ref{svpbmt}. Bits 60--54 are reserved for future standard use. All of these bits must be zeroed by software for forward compatibility. If any of these bits are set, a page-fault exception is raised. @@ -1920,9 +1923,10 @@ is untranslated. \begin{figure*}[h!] {\footnotesize \begin{center} -\begin{tabular}{cF@{}F@{}F@{}F@{}F@{}Fcccccccc} +\begin{tabular}{cF@{}F@{}F@{}F@{}F@{}F@{}Fcccccccc} \instbit{63} & -\instbitrange{62}{54} & +\instbitrange{62}{61} & +\instbitrange{60}{54} & \instbitrange{53}{37} & \instbitrange{36}{28} & \instbitrange{27}{19} & @@ -1938,6 +1942,7 @@ is untranslated. \instbit{0} \\ \hline \multicolumn{1}{|c|}{N} & +\multicolumn{1}{c|}{PBMT} & \multicolumn{1}{c|}{\it Reserved} & \multicolumn{1}{c|}{PPN[3]} & \multicolumn{1}{c|}{PPN[2]} & @@ -1953,7 +1958,7 @@ is untranslated. \multicolumn{1}{c|}{R} & \multicolumn{1}{c|}{V} \\ \hline -1 & 9 & 17 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ +1 & 2 & 7 & 17 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ \end{tabular} \end{center} } @@ -2061,14 +2066,11 @@ is untranslated. \begin{figure*}[h!] {\footnotesize \begin{center} -\begin{tabular}{c@{}Y@{}F@{}F@{}F@{}F@{}F@{}Wcccccccc} +\begin{tabular}{c@{}F@{}Y@{}T@{}Wcccccccc} \instbit{63} & -\instbitrange{62}{54} & -\instbitrange{53}{46} & -\instbitrange{45}{37} & -\instbitrange{36}{28} & -\instbitrange{27}{19} & -\instbitrange{18}{10} & +\instbitrange{62}{61} & +\instbitrange{60}{54} & +\instbitrange{53}{10} & \instbitrange{9}{8} & \instbit{7} & \instbit{6} & @@ -2080,12 +2082,9 @@ is untranslated. \instbit{0} \\ \hline \multicolumn{1}{|c|}{N} & +\multicolumn{1}{c|}{PBMT} & \multicolumn{1}{c|}{\it Reserved} & -\multicolumn{1}{c|}{PPN[4]} & -\multicolumn{1}{c|}{PPN[3]} & -\multicolumn{1}{c|}{PPN[2]} & -\multicolumn{1}{c|}{PPN[1]} & -\multicolumn{1}{c|}{PPN[0]} & +\multicolumn{1}{c|}{PPN} & \multicolumn{1}{c|}{RSW} & \multicolumn{1}{c|}{D} & \multicolumn{1}{c|}{A} & @@ -2096,7 +2095,23 @@ is untranslated. \multicolumn{1}{c|}{R} & \multicolumn{1}{c|}{V} \\ \hline -1 & 9 & 8 & 9 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ +1 & 2 & 7 & 44 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ +\end{tabular} + +\begin{tabular}{@{}F@{}F@{}F@{}F@{}F} +\instbitrange{53}{46} & +\instbitrange{45}{37} & +\instbitrange{36}{28} & +\instbitrange{27}{19} & +\instbitrange{18}{10} \\ +\hline +\multicolumn{1}{|c|}{PPN[4]} & +\multicolumn{1}{c|}{PPN[3]} & +\multicolumn{1}{c|}{PPN[2]} & +\multicolumn{1}{c|}{PPN[1]} & +\multicolumn{1}{c|}{PPN[0]} \\ +\hline +8 & 9 & 9 & 9 & 9 \\ \end{tabular} \end{center} } @@ -2248,3 +2263,104 @@ algorithm in Section~\ref{sv32algorithm}, except that: However, in case finer-grained intermediate page size support proves not to be useful, we have chosen to standardize only 64KiB support as a first step. \end{commentary} + +\chapter{``Svpbmt'' Standard Extension for Page-Based Memory Types, Version 0.1} +\label{svpbmt} + +In Sv39, Sv48, and Sv57, bits 62--61 of a leaf page table entry indicate the use +of page-based memory types that override the PMA(s) for the associated memory +pages. The encoding for the PBMT bits is captured in Table~\ref{pbmt}. + +\begin{table*}[h!] +\begin{center} +\begin{tabular}{|r|l|} +\hline +Value & Requested Memory Attributes \\ +\hline +0 & None \\ +1 & Non-cacheable, idempotent, weakly-ordered (RVWMO or RVTSO), main memory \\ +2 & Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O \\ +3 & {\em Reserved for future standard use} \\ +\hline +\end{tabular} +\end{center} +\caption{Encodings for the PBMT field in Sv39, Sv48, and Sv57 PTEs. Attributes +not mentioned are inherited from the PMA associated with the physical address.} +\label{pbmt} +\end{table*} + +\begin{commentary} +Future extensions may provide more and/or finer-grained control over which PMAs +can be overridden. +\end{commentary} + +For non-leaf PTEs, bits 62--61 are reserved for future standard use and must be +cleared by software for forward compatibility. + +If the underlying physical memory attribute for a page is main memory and +the page has PBMT=0 or PBMT=1, or if the underlying physical memory attribute +for a page is I/O and the page has PBMT=0 or PBMT=2, then accesses to that page +obey the same memory ordering rules normally applied to accesses to that +physical page. + +If the underlying physical memory attribute for a page is I/O, and the page has +PBMT=1, then then accesses to that page obey RVWMO. Accesses to such pages are +considered main memory rather than I/O for the purposes of FENCE, {\em.aq}, and +{\em.rl}. + +If the underlying physical memory attribute for a page is main memory, and the +page has PBMT=2, then accesses to that page obey strong channel 0 I/O ordering +rules with respect to other accesses to physical main memory and to other +accesses to pages with PBMT=2. Furthermore, accesses to such pages are +considered I/O rather than main memory for the purposes of FENCE, {\em.aq}, and +{\em.rl}. + +When Svpbmt is used with non-zero PBMT encodings, +it is possible for multiple virtual aliases of the same +physical page to exist simultaneously with different memory attributes. It is +also possible for a U-mode or S-mode mapping through a PTE with Svpbmt enabled +to observe different memory attributes for a given region of physical memory +than a concurrent access to the same page performed by M-mode or when +MODE=Bare. In such cases, there may be a loss of coherence and/or of normal +RVWMO, RVTSO, or I/O ordering semantics, and platform-specific mechanisms must +be used to restore coherence and memory ordering. + +\begin{commentary} +For example, a cacheable access may be issued at the same time as a +non-cacheable access to the same physical memory address. In this case, +if the former is performed first in the global memory order, then it will +be evicted from the cache by the latter. If on the other hand the cacheable +access appears after the non-cacheable access, then the former may remain +cached as it normally would. + +Likewise, accesses performed under memory indicating the non-idempotent +attribute must not be merged with idempotent accesses to the same region +in flight at the same time, as the non-idempotency of the former must +be respected. This is not expected to be a common situation. + +Note that Svpbmt cannot be used to completely prevent speculative reads from +being performed to a region of memory for which the PMAs indicate idempotence, +as speculation can still be performed via M-mode or via Bare mappings, which do +not use the PBMTs. Platform-specific mechanisms must be used to avoid this +form of conflict. +\end{commentary} + +\begin{commentary} +A device driver written to rely on I/O strong ordering rules will not +operate correctly if the address range is mapped as main memory by the +page-based memory types. As such, this configuration is discouraged. + +It will often still be useful to map physical I/O regions using PBMT=1 so that +write combining and speculative accesses can be performed. Such optimizations +will likely improve performance when applied with adequate care. +\end{commentary} + +When two-stage address translation is enabled within the H extension, the +page-based memory types are also applied in two stages. First, if +{\tt hgatp}.MODE is not equal to zero, the G-stage PTE PBMT bits are applied to +the attributes in the PMA to produce an intermediate set of attributes. +Otherwise, the PMAs serve as the intermediate attributes. Second, if +{\tt vsatp}.MODE is not equal to zero, the VS-stage PTE PBMT bits are applied +to the intermediate attributes to produce the final set of attributes used by +accesses to the page in question. Otherwise, the intermediate attributes are +used as the final set of attributes. |