diff options
| -rw-r--r-- | src/hypervisor.tex | 74 | ||||
| -rw-r--r-- | src/priv-preface.tex | 1 | ||||
| -rw-r--r-- | src/supervisor.tex | 157 |
3 files changed, 205 insertions, 27 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index a115650..0b8e82d 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -1076,7 +1076,7 @@ wide as 34 bits, and {\tt htval} reports bits 33:2 of the address. This shift-by-2 encoding of guest physical addresses matches the encoding of physical addresses in PMP address registers (Section~\ref{sec:pmp}) and in page table entries (Sections \ref{sec:sv32}, \ref{sec:sv39}, -and~\ref{sec:sv48}). +\ref{sec:sv48}, and~\ref{sec:sv57}). If the least-significant two bits of a faulting guest physical address are needed, these bits are ordinarily the same as the least-significant @@ -1187,7 +1187,7 @@ in HS-mode will raise an illegal instruction exception. } \vspace{-0.1in} \caption{Hypervisor guest address translation and protection register -{\tt hgatp} when HSXLEN=64, for MODE values Bare, Sv39x4, and Sv48x4.} +{\tt hgatp} when HSXLEN=64, for MODE values Bare, Sv39x4, Sv48x4, and Sv57x4.} \label{rv64hgatp} \end{figure} @@ -1202,12 +1202,10 @@ In this case, the remaining fields in {\tt hgatp} must be set to zeros. When HSXLEN=32, the only other valid setting for MODE is Sv32x4, which is a modification of the usual Sv32 paged virtual-memory scheme, extended to support 34-bit guest physical addresses. -When HSXLEN=64, modes Sv39x4 and Sv48x4 are defined as modifications of the Sv39 and -Sv48 paged virtual-memory schemes. +When HSXLEN=64, modes Sv39x4, Sv48x4, and Sv57x4 are defined as modifications of the +Sv39, Sv48, and Sv57 paged virtual-memory schemes. All of these paged virtual-memory schemes are described in Section~\ref{sec:guest-addr-translation}. -An additional scheme for HSXLEN=64, Sv57x4, may be defined in a later version of this -specification. The remaining MODE settings when HSXLEN=64 are reserved for future use and may define different interpretations of the other fields in {\tt hgatp}. @@ -1231,7 +1229,7 @@ Value & Name & Description \\ 1--7 & --- & {\em Reserved} \\ 8 & Sv39x4 & Page-based 41-bit virtual addressing (2-bit extension of Sv39). \\ 9 & Sv48x4 & Page-based 50-bit virtual addressing (2-bit extension of Sv48). \\ -10 & {\em Sv57x4} & {\em Reserved for page-based 59-bit virtual addressing.} \\ +10 & Sv57x4 & Page-based 59-bit virtual addressing (2-bit extension of Sv57). \\ 11--15 & --- & {\em Reserved} \\ \hline \end{tabular} @@ -1249,7 +1247,7 @@ Instead, the fields of {\tt hgatp} are {\warl} in the normal way, when so indicated. As explained in Section~\ref{sec:guest-addr-translation}, for the paged -virtual-memory schemes (Sv32x4, Sv39x4, and Sv48x4), the root page table is +virtual-memory schemes (Sv32x4, Sv39x4, Sv48x4, and Sv57x4), the root page table is 16~KiB and must be aligned to a 16-KiB boundary. In these modes, the lowest two bits of the physical page number (PPN) in {\tt hgatp} always read as zeros. @@ -1263,8 +1261,8 @@ back the value in {\tt hgatp} to see which bit positions in the VMID field hold a one. The least-significant bits of VMID are implemented first: that is, if VMIDLEN~$>$~0, VMID[VMIDLEN-1:0] is writable. -The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4 -and Sv48x4. +The maximal value of VMIDLEN, termed VMIDMAX, is 7 for Sv32x4 or 14 for Sv39x4, +Sv48x4, and Sv57x4. The {\tt hgatp} register is considered {\em active} for the purposes of the address-translation algorithm when the effective privilege mode is VS-mode or @@ -1783,7 +1781,7 @@ Section~\ref{sec:two-stage-translation}). } \vspace{-0.1in} \caption{Virtual supervisor address translation and protection register {\tt vsatp} when VSXLEN=64, for MODE -values Bare, Sv39, and Sv48.} +values Bare, Sv39, Sv48, and Sv57.} \label{rv64vsatpreg} \end{figure*} @@ -2452,9 +2450,9 @@ is Bare, guest physical addresses are equal to supervisor physical addresses without modification, and no memory protection applies in the trivial translation of guest physical addresses to supervisor physical addresses. -When {\tt hgatp}.MODE specifies a translation scheme of Sv32x4, Sv39x4, or -Sv48x4, G-stage address translation is a variation on the usual -page-based virtual address translation scheme of Sv32, Sv39, or Sv48, +When {\tt hgatp}.MODE specifies a translation scheme of Sv32x4, Sv39x4, +Sv48x4, or Sv57x4, G-stage address translation is a variation on the usual +page-based virtual address translation scheme of Sv32, Sv39, Sv48, or Sv57, respectively. In each case, the size of the incoming address is widened by 2~bits (to 34, 41, or 50 bits). @@ -2462,10 +2460,11 @@ To accommodate the 2~extra bits, the root page table (only) is expanded by a factor of four to be 16~KiB instead of the usual 4~KiB. Matching its larger size, the root page table also must be aligned to a 16~KiB boundary instead of the usual 4~KiB page boundary. -Except as noted, all other aspects of Sv32, Sv39, or Sv48 are adopted unchanged -for G-stage translation. +Except as noted, all other aspects of Sv32, Sv39, Sv48, or Sv57 are adopted +unchanged for G-stage translation. Non-root page tables and all page table entries (PTEs) have the same formats as -documented in Sections \ref{sec:sv32}, \ref{sec:sv39}, and~\ref{sec:sv48}. +documented in Sections \ref{sec:sv32}, \ref{sec:sv39}, \ref{sec:sv48}, +and~\ref{sec:sv57}. For Sv32x4, an incoming guest physical address is partitioned into a virtual page number (VPN) and page offset as shown in Figure~\ref{sv32x4va}. @@ -2561,6 +2560,41 @@ exception occurs. \label{sv48x4va} \end{figure*} +For Sv57x4, an incoming guest physical address is partitioned as shown in +Figure~\ref{sv57x4va}. +This partitioning is identical to that for an Sv57 virtual address as depicted +in Figure~\ref{sv57va} (page~\pageref{sv57va}), except with 2 more bits at the +high end in VPN[3]. +Address bits 63:50 must all be zeros, or else a guest-page-fault +exception occurs. + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}S@{}R@{}R@{}R@{}R@{}S} +\instbitrange{58}{50} & +\instbitrange{49}{39} & +\instbitrange{38}{30} & +\instbitrange{29}{21} & +\instbitrange{20}{12} & +\instbitrange{11}{0} \\ +\hline +\multicolumn{1}{|c|}{VPN[4]} & +\multicolumn{1}{c|}{VPN[3]} & +\multicolumn{1}{c|}{VPN[2]} & +\multicolumn{1}{c|}{VPN[1]} & +\multicolumn{1}{c|}{VPN[0]} & +\multicolumn{1}{c|}{page offset} \\ +\hline +11 & 9 & 9 & 9 & 9 & 12 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Sv57x4 virtual address (guest physical address).} +\label{sv57x4va} +\end{figure*} + \begin{commentary} The page-based G-stage address translation scheme for RV32, Sv32x4, is defined to support a 34-bit guest physical address so that an RV32 hypervisor @@ -2583,9 +2617,9 @@ addresses (Sv48) or falling back to emulating the larger address space using shadow page tables. \end{commentary} -The conversion of an Sv32x4, Sv39x4, or Sv48x4 guest physical address is -accomplished with the same algorithm used for Sv32, Sv39, or Sv48, as presented -in Section~\ref{sv32algorithm}, except that: +The conversion of an Sv32x4, Sv39x4, Sv48x4, or Sv57x4 guest physical address is +accomplished with the same algorithm used for Sv32, Sv39, Sv48, or Sv57, as +presented in Section~\ref{sv32algorithm}, except that: \begin{compactitem} \item {\tt hgatp} substitutes for the usual {\tt satp}; diff --git a/src/priv-preface.tex b/src/priv-preface.tex index 821ff32..8e5e4e1 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -74,6 +74,7 @@ Additionally, the following compatible changes have been made since version \item Slightly relaxed the atomicity requirement for A and D bit updates performed by the implementation. \item Clarify the architectural behavior of address-translation caches +\item Added Sv57 and Sv57x4 address translation modes. \item Software breakpoint exceptions are permitted to write either 0 or the PC to {\em x}\/{\tt tval}. \item Clarified that bare S-mode need not support the SFENCE.VMA instruction. diff --git a/src/supervisor.tex b/src/supervisor.tex index 76370b0..3d300aa 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -976,7 +976,7 @@ main memory be representable. \vspace{-0.1in} \caption{% Supervisor address translation and protection register {\tt satp} -when SXLEN=64, for MODE values Bare, Sv39, and Sv48.% +when SXLEN=64, for MODE values Bare, Sv39, Sv48, and Sv57.% } \label{rv64satp} \end{figure} @@ -1017,9 +1017,9 @@ all patterns of the existing MODE field have already been allocated. When SXLEN=32, the only other valid setting for MODE is Sv32, a paged virtual-memory scheme described in Section~\ref{sec:sv32}. -When SXLEN=64, two paged virtual-memory schemes are defined: Sv39 and Sv48, -described in Sections~\ref{sec:sv39} and \ref{sec:sv48}, respectively. -Two additional schemes, Sv57 and Sv64, will be defined in a later version +When SXLEN=64, three paged virtual-memory schemes are defined: Sv39, Sv48, and Sv57, +described in Sections~\ref{sec:sv39}, \ref{sec:sv48}, and \ref{sec:sv57}, respectively. +One additional scheme, Sv64, will be defined in a later version of this specification. The remaining MODE settings are reserved for future use and may define different interpretations of the other fields in {\tt satp}. @@ -1047,7 +1047,7 @@ Value & Name & Description \\ 1--7 & --- & {\em Reserved for standard use} \\ 8 & Sv39 & Page-based 39-bit virtual addressing (see Section~\ref{sec:sv39}). \\ 9 & Sv48 & Page-based 48-bit virtual addressing (see Section~\ref{sec:sv48}). \\ -10 & {\em Sv57} & {\em Reserved for page-based 57-bit virtual addressing.} \\ +10 & Sv57 & Page-based 57-bit virtual addressing (see Section~\ref{sec:sv57}). \\ 11 & {\em Sv64} & {\em Reserved for page-based 64-bit virtual addressing.} \\ 12--13 & --- & {\em Reserved for standard use} \\ 14--15 & --- & {\em Designated for custom use} \\ @@ -1064,7 +1064,7 @@ determined by writing one to every bit position in the ASID field, then reading back the value in {\tt satp} to see which bit positions in the ASID field hold a one. The least-significant bits of ASID are implemented first: that is, if ASIDLEN~$>$~0, ASID[ASIDLEN-1:0] is writable. The maximal value -of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39 and Sv48. +of ASIDLEN, termed ASIDMAX, is 9 for Sv32 or 16 for Sv39, Sv48, and Sv57. \begin{commentary} For many applications, the choice of page size has a substantial @@ -1829,7 +1829,9 @@ cost. For many systems, \wunits{512}{GiB} of virtual-address space is ample, and so Sv39 suffices. Sv48 increases the virtual address space to \wunits{256}{TiB}, but increases the physical memory capacity dedicated to page tables, the latency of page-table traversals, and -the size of hardware structures that store virtual addresses. +the size of hardware structures that store virtual addresses. Sv57 increases +the virtual address space, page table capacity requirement, and translation +latency even further. \end{commentary} \subsection{Addressing and Memory Protection} @@ -2106,3 +2108,144 @@ aligned. The algorithm for virtual-to-physical address translation is the same as in Section~\ref{sv32algorithm}, except LEVELS equals 4 and PTESIZE equals 8. + +\section{Sv57: Page-Based 57-bit Virtual-Memory System} +\label{sec:sv57} + +This section describes a simple paged virtual-memory system designed +for RV64 systems, which supports 57-bit virtual address spaces. Sv57 +is intended for systems for which a 48-bit virtual address space is +insufficient. It closely follows the design of Sv48, simply adding an +additional level of page table, and so this chapter only details the +differences between the two schemes. + +Implementations that support Sv57 must also support Sv48. + +\begin{commentary} +Systems that support Sv57 can also support Sv48 at essentially no cost, and so +should do so to maintain compatibility with supervisor software that assumes +Sv48. +\end{commentary} + +\subsection{Addressing and Memory Protection} + +Sv57 implementations support a 57-bit virtual address space, divided +into \wunits{4}{KiB} pages. An Sv57 address is partitioned as +shown in Figure~\ref{sv57va}. +Instruction fetch addresses and load and store effective addresses, +which are 64 bits, must have bits 63--57 all equal to bit 56, or else +a page-fault exception will occur. The 45-bit VPN is translated into a +44-bit PPN via a five-level page table, while the 12-bit page offset +is untranslated. + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}S@{}S@{}S@{}S@{}S@{}S} +\instbitrange{56}{48} & +\instbitrange{47}{39} & +\instbitrange{38}{30} & +\instbitrange{29}{21} & +\instbitrange{20}{12} & +\instbitrange{11}{0} \\ +\hline +\multicolumn{1}{|c|}{VPN[4]} & +\multicolumn{1}{c|}{VPN[3]} & +\multicolumn{1}{c|}{VPN[2]} & +\multicolumn{1}{c|}{VPN[1]} & +\multicolumn{1}{c|}{VPN[0]} & +\multicolumn{1}{c|}{page offset} \\ +\hline +9 & 9 & 9 & 9 & 9 & 12 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Sv57 virtual address.} +\label{sv57va} +\end{figure*} + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}R@{}S@{}S@{}S@{}S@{}S} +\instbitrange{55}{48} & +\instbitrange{47}{39} & +\instbitrange{38}{30} & +\instbitrange{29}{21} & +\instbitrange{20}{12} & +\instbitrange{11}{0} \\ +\hline +\multicolumn{1}{|c|}{PPN[4]} & +\multicolumn{1}{c|}{PPN[3]} & +\multicolumn{1}{c|}{PPN[2]} & +\multicolumn{1}{c|}{PPN[1]} & +\multicolumn{1}{c|}{PPN[0]} & +\multicolumn{1}{c|}{page offset} \\ +\hline +8 & 9 & 9 & 9 & 9 & 12 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Sv57 physical address.} +\label{sv57pa} +\end{figure*} + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}Y@{}F@{}F@{}F@{}F@{}F@{}Wcccccccc} +\instbitrange{63}{54} & +\instbitrange{53}{46} & +\instbitrange{45}{37} & +\instbitrange{36}{28} & +\instbitrange{27}{19} & +\instbitrange{18}{10} & +\instbitrange{9}{8} & +\instbit{7} & +\instbit{6} & +\instbit{5} & +\instbit{4} & +\instbit{3} & +\instbit{2} & +\instbit{1} & +\instbit{0} \\ +\hline +\multicolumn{1}{|c|}{\it Reserved} & +\multicolumn{1}{c|}{PPN[4]} & +\multicolumn{1}{c|}{PPN[3]} & +\multicolumn{1}{c|}{PPN[2]} & +\multicolumn{1}{c|}{PPN[1]} & +\multicolumn{1}{c|}{PPN[0]} & +\multicolumn{1}{c|}{RSW} & +\multicolumn{1}{c|}{D} & +\multicolumn{1}{c|}{A} & +\multicolumn{1}{c|}{G} & +\multicolumn{1}{c|}{U} & +\multicolumn{1}{c|}{X} & +\multicolumn{1}{c|}{W} & +\multicolumn{1}{c|}{R} & +\multicolumn{1}{c|}{V} \\ +\hline +10 & 8 & 9 & 9 & 9 & 9 & 2 & 1 & 1 & 1 & 1 & 1 & 1 & 1 & 1\\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Sv57 page table entry.} +\label{sv57pte} +\end{figure*} + +The PTE format for Sv57 is shown in Figure~\ref{sv57pte}. Bits 63--54 and 9--0 +have the same meaning as for Sv39. Any level of PTE may be a leaf +PTE, so in addition to \wunits{4}{KiB} pages, Sv57 supports +\wunits{2}{MiB} {\em megapages}, \wunits{1}{GiB} {\em gigapages}, +\wunits{512}{GiB} {\em terapages}, and \wunits{256}{TiB} {\em petapages}, +each of which must be virtually and physically aligned to a boundary equal +to its size. A page-fault exception is raised if the physical address is +insufficiently aligned. + +The algorithm for virtual-to-physical address translation is the same +as in Section~\ref{sv32algorithm}, except LEVELS equals 5 and PTESIZE +equals 8. |