diff options
| -rw-r--r-- | src/machine.adoc | 10 | ||||
| -rw-r--r-- | src/supervisor.adoc | 10 |
2 files changed, 10 insertions, 10 deletions
diff --git a/src/machine.adoc b/src/machine.adoc index 7918d22..a2b90a7 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -1370,7 +1370,7 @@ and can be written with a given value. Any CSR write takes effect after the writing instruction has otherwise completed. The `mcycle` CSR may be shared between harts on the same core, in which case writes to `mcycle` will be visible to those harts. The platform should provide a mechanism -to indicate which harts share an ` mcycle` CSR. +to indicate which harts share an `mcycle` CSR. The hardware performance monitor includes 29 additional 64-bit event counters, `mhpmcounter3`-`mhpmcounter31`. The event selector CSRs, @@ -1513,7 +1513,7 @@ The RISC-V user ISA was designed to support many possible privileged system environments and so we did not want to infect the user-level ISA with any OS-dependent features. The RISC-V CSR swap instructions can quickly save/restore values to the `mscratch` register. Unlike the MIPS -design, the OS can rely on holding a value in the ` mscratch` register +design, the OS can rely on holding a value in the `mscratch` register while the user context is running. ==== @@ -1558,7 +1558,7 @@ include::images/bytefield/mepcreg.adoc[] The `mcause` register is an MXLEN-bit read-write register formatted as shown in <<mcausereg>>. When a trap is taken into -M-mode, ` mcause` is written with a code indicating the event that +M-mode, `mcause` is written with a code indicating the event that caused the trap. Otherwise, `mcause` is never written by the implementation, though it may be explicitly written by software. @@ -2066,7 +2066,7 @@ occasional spurious timer interrupt than to poll MTIP until it falls. ==== In RV32, memory-mapped writes to `mtimecmp` modify only one 32-bit part -of the register. The following code sequence sets a 64-bit ` mtimecmp` +of the register. The following code sequence sets a 64-bit `mtimecmp` value without spuriously generating a timer interrupt due to the intermediate value of the comparand: @@ -2929,7 +2929,7 @@ any address `y<pmpaddr~0~`. [NOTE] ==== -If `pmpaddr~i-1~≥``pmpaddr~i~`` and `pmpcfg~i~.A`=TOR, then PMP entry _i_ matches no addresses. +If `pmpaddr~i-1~≥``pmpaddr~i~``` and `pmpcfg~i~.A`=TOR, then PMP entry _i_ matches no addresses. ==== Although the PMP mechanism supports regions as small as four bytes, diff --git a/src/supervisor.adoc b/src/supervisor.adoc index 14755e4..a7297b9 100644 --- a/src/supervisor.adoc +++ b/src/supervisor.adoc @@ -302,7 +302,7 @@ in `sie`, then reading back to see which bit positions hold a one. [NOTE] ==== -The `sip` and `sie` registers are subsets of the `mip` and ` mie` +The `sip` and `sie` registers are subsets of the `mip` and `mie` registers. Reading any implemented field, or writing any writable field, of `sip`/`sie` effects a read or write of the homonymous field of `mip`/`mie`. @@ -351,7 +351,7 @@ an exception when executing in U-mode. Hence, they are effectively ==== The setting of a bit in `mcounteren` does not affect whether the corresponding bit in `scounteren` is writable. However, U-mode may only -access a counter if the corresponding bits in ` scounteren` and +access a counter if the corresponding bits in `scounteren` and `mcounteren` are both set. ==== @@ -360,7 +360,7 @@ access a counter if the corresponding bits in ` scounteren` and The `sscratch` register is an SXLEN-bit read/write register, dedicated for use by the supervisor. Typically, `sscratch` is used to hold a pointer to the hart-local supervisor context while the hart is executing -user code. At the beginning of a trap handler, ` sscratch` is swapped +user code. At the beginning of a trap handler, `sscratch` is swapped with a user register to provide an initial working register. .Supervisor Scratch Register @@ -397,7 +397,7 @@ include::images/bytefield/epcreg.edn[] The `scause` register is an SXLEN-bit read-write register formatted as shown in <<scausereg>>. When a trap is taken into -S-mode, ` scause` is written with a code indicating the event that +S-mode, `scause` is written with a code indicating the event that caused the trap. Otherwise, `scause` is never written by the implementation, though it may be explicitly written by software. @@ -556,7 +556,7 @@ addresses and the value 0. It need not be capable of holding all possible invalid addresses. Prior to writing `stval`, implementations may convert an invalid address into some other invalid address that `stval` is capable of holding. If the feature to return the faulting -instruction bits is implemented, ` stval` must also be able to hold all +instruction bits is implemented, `stval` must also be able to hold all values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller of SXLEN and ILEN. |